enjoy-digital / litedram

Small footprint and configurable DRAM core

enjoy-digital/litedram Issues

Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO
Updated 17 days ago2
Adding support to gowin phys in litedram.gen?
Updated a month ago
LiteDRAMDMAWriter sinks data when not enabled
Updated a month ago2
LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.
Updated a month ago1
Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file,
Updated 2 months ago
GENDDRPHY support?
Updated 4 months ago
litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)
Updated 7 months ago5
DE10-Lite Memory initialization failed
Updated 9 months ago
Underclocking DRAM controler to increase access time
Updated 9 months ago
LiteDRAM core targeting DDR3 issues activate command twice for a write operation
Updated 9 months ago
Axi port write data error
Updated a year ago8
Carrying out the LiteDRAM standalone core initialization manually, through wishbone ctrl interface
Updated a year ago5
Is it possible to adjust burst-length in order to widen data path ?
Updated a year ago
DDR3 Memory on Kintex7 325T based board randomly fails
Closed 2 years ago48
wb_ctrl ports of ECP5 litedram_core generated for OrangeCrab02-25F failing when user_ports is native
Updated a year ago
LiteDRAMDMAWriter cannot write accurate data to a specific address?
Updated a year ago
AxSIZE mismatch?
Updated a year ago1
ulx3s example does not work
Updated a year ago3
Setting for user_clk
Updated a year ago1
Generate liteDRAM verilog file
Closed a year ago4
DDR4 reads without DQS at high speeds?
Updated a year ago1
Simulation issue, Arty S7 (Beginner)
Closed 2 years ago9
--top-module 'sim' was not found in the design
Updated a year ago5
Need Help Generating Verilog DRAM controller, while maininting module hiraerachies.
Closed a year ago1
DMA AXI BUG
Closed a year ago1
Corresponding verilog testbench for ASIC
Updated a year ago1
submodules verilog
Updated a year ago2
sdram_init() vs. init_sequence()
Updated a year ago
Problem with adding new LPDDR module: MT46H128M16
Closed 2 years ago1
Typical litedram-L2 port sizes
Updated 2 years ago
Help generating DDR3 Verilog module for Digilent NexysVideo Artix-7 FPGA
Updated 2 years ago3
QuarterRateGENSDRPHY
Updated 2 years ago2
New to LiteDRAM
Closed 2 years ago2
Why are CL and CWL not included as speedgrade parameters in the module class?
Updated 2 years ago1
LiteDRAM USPDDRPHY unable to meet DDR4 timing requirements?
Updated 2 years ago8
Unable to run Litedram on Digilent Genesys2
Closed 2 years ago6
DDR4 Memtest Failed
Closed 2 years ago3
Strategy steering: Best way to stream data into a custom accelerator when litedram is being used inside Litex SoC?
Closed 2 years ago4
Help creating verilog module to go from Wishbone4 to Litedram native port
Closed 2 years ago1
ULX4M DM signal is not connected to DQS group
Closed 2 years ago2
memtest fails on arty depending on read leveling outcome
Closed 2 years ago3
Initialization failed on Artix after e5e3b6c
Closed 2 years ago5
Possible to Create Software Initialization File Without Regenerating Core?
Closed 2 years ago1
Figure out how to hook LiteDRAM to the WDDR PHY
Updated 2 years ago1
generate user interface
Closed 2 years ago1
LDDR5 Support
Closed 2 years ago2
The MAX sys_clk_freq supported of DDR4
Closed 3 years ago1
Changes to tREFI ignored
Closed 3 years ago5
litedram does not use full address space?
Closed 3 years ago7
sdram.c:39:37: error: static declaration of 'cdelay' follows non-static declaration
Closed 3 years ago1