Giters
enjoy-digital
/
litex
Build your hardware, easily!
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Stargazers:
2717
Watchers:
97
Issues:
768
Forks:
528
enjoy-digital/litex Issues
Can't boot linux with MAIN_RAM sizes above 512mb
Updated
5 days ago
Comments count
55
Native windows Vivado and WSL2 Litex build fails to find toolchain
Updated
7 days ago
Comments count
2
Upgrade of the CV32E40P to the openhwgroup repo ?
Updated
8 days ago
Comments count
7
Issues with main memory > 1GB
Updated
11 days ago
Comments count
1
RISC-V debug module support for CV32E40P/41P ?
Updated
19 days ago
WSL2 Debian Gowin Toolchain Path
Updated
a month ago
Comments count
2
Trying to interact with UART via Rust binary (stuck at liftoff)
Updated
a month ago
Comments count
2
Loading binary hangs up
Updated
a month ago
Comments count
3
Weird builder args behaviour
Updated
a month ago
default FIFO depth for video is too large for some devices
Updated
a month ago
Liteeth: Broken constraints
Updated
a month ago
Comments count
4
How to set multi-level sequential trigger in litescope ?
Updated
a month ago
Comments count
1
liteeth linux driver performances
Updated
a month ago
Comments count
6
UART output not displayed
Updated
a month ago
Comments count
2
litex_sim of CV32E41P is stuck
Updated
a month ago
Comments count
2
Add example for embedding a LiteX SOC into Vivado project for Zynq
Updated
2 months ago
Comments count
4
Restrict bus crossbar access by region mode
Updated
2 months ago
Generated DTS lacks root compatible and model properties
Updated
2 months ago
Comments count
3
vexriscv_smp: only 32 CSR locations supported with current mem_mam
Closed
2 months ago
Comments count
4
Support of MIPS cores
Updated
2 months ago
Support of IO-Link
Updated
3 months ago
NuttX + LiteEth: Potential regression when using Hybrid Etherbone/Ethernet.
Closed
3 months ago
Comments count
8
Failed to modify “boot.c” and the riscv64-unknown-elf/bin/ld report an error “undefined reference to `__heap_start'”
Closed
4 months ago
Comments count
4
Support of RapidIO
Updated
3 months ago
Support of Interlaken protocol
Updated
3 months ago
new Spartan6 programmer
Updated
3 months ago
Tang Primer 20k dram issues
Updated
3 months ago
Comments count
23
Xilinx Zynq-7000 digilent_zedboard: workflow failed with meson ERROR: No statements in code.
Updated
3 months ago
tang Nano 9k no uart out
Updated
3 months ago
Comments count
2
Allow CSR paging 0x400
Closed
4 months ago
Comments count
2
Windows based build cannot find toolchain support
Closed
4 months ago
Comments count
3
Unexpected behaviour of printf
Updated
4 months ago
Comments count
9
No serial output on tang 9k when selecting other sys-clk-freq
Updated
4 months ago
Comments count
11
Clock domain crossing for peripherals
Updated
4 months ago
Comments count
3
How to use Verilator's "forcable" signals
Updated
4 months ago
netboot
Closed
4 months ago
Comments count
2
brew cask install tuntap
Updated
4 months ago
Missing VCCIO settings for ECP5 when using diamond toolchain
Updated
4 months ago
Wishbone bus high latency in read on Vexriscv CPU "minimal" variant and read/write on others CPU.
Updated
4 months ago
Comments count
3
LiteScope: more help needed
Updated
4 months ago
Comments count
5
[Feature request] Support of pmem / Non Volatile Memory
Updated
4 months ago
Comments count
1
[Feature request] Support to run WebAssembly on FPGA
Updated
4 months ago
Comments count
1
Help with LiteScope and jtagbone
Closed
5 months ago
Comments count
5
Make Error *** No rule to make target 'boot-helper.o', needed by 'bios.elf'. Stop. Neorv32 core TUL PYNQ Z2
Closed
5 months ago
Comments count
1
Html doc not generating for TUL PYNQ Z2
Closed
5 months ago
Comments count
2
What generates `ctrl_bus_errors_read`?
Closed
5 months ago
Comments count
1
Python minimum requirement should be updated.
Closed
5 months ago
Comments count
1
The non-ASCII character "…" in README.md may cause failure in setup
Closed
5 months ago
Comments count
1
Add 64-bit addressing support.
Closed
5 months ago
Comments count
3
Litex sometimes generates unsimulatable verilog
Closed
5 months ago
Comments count
2
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