enjoy-digital / litex_mister_test

Simplification test of MiSTer with LiteX to try to help/contribute to MiSTeX project.

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Simplification test of MiSTer with LiteX to try to help/contribute to MiSTeX project.

Language:Verilog 42.1%Language:SystemVerilog 25.7%Language:VHDL 22.3%Language:Python 7.5%Language:Tcl 2.4%