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This repository contains a series of Verilog codes for the course UE22CS251A (DDCO).
Project to Design and Implement a 16-bit Shift Adder (Serial Adder) using Verilog.
This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
Digital Design and Computer Organisation Mini-project
Project to Design and Implement a 16-bit Barrel Shifter using Verilog.
Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)