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A bunch of MIPS (assembly) programming exercises and problems done in college as a part of the course Computer Architecture (CS F342).
Compilation of my Computer Architrcture and Verilog Courses at UW. Documentation for the code included in the individual directories.
32-bit 5-stage pipelined RISC-V CPU (RV32I) in Verilog HDL. Supports ADD, SUB, AND, OR, LW, SW, BEQ, BNE with hazard handling (forwarding, stalls, flushes). Verified using testbenches and GTKWave, achieving CPI ≈ 1.0 on hazard-free execution.
Lab assignments and some practise done for the Computer Architecture course at BITS Pilani
Nand2Tetris - Building a simulated Computer System from First Principle