tanbour's repositories
gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
FPGA-FOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。
fpga_pio
An attempt to recreate the RP2040 PIO in an FPGA
rggen-verilog
Verilog writer plugin for RgGen
scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Formal_Verification
Coverage Closure and Bug Hunt Project
QSPI_FOR_SOC
QSPI for SoC
UART_VLC_Transmission
UART (9600/115200) to VLC (RS code/Manchester code/8x Sampling Syncronization)
wujian100_open
IC design and development should be faster,simpler and more reliable
antikernel
The Antikernel operating system project
Functional-Safety-Notes
基于Xilinx平台的功能安全笔记
antikernel-ipcores
FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
Exploring-Zynq-MPSoC-CN
Exploring Zynq ® MPSoC Chinese
cores
Various HDL (Verilog) IP Cores
firrtl
Flexible Intermediate Representation for RTL
chisel3
Chisel 3
qspiflash
A set of Wishbone Controlled SPI Flash Controllers
swerv_sim
simulation env for swerv_th1, which is base on vcs & verdi
cocotb
Coroutine Co-simulation Test Bench
swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
Design-Verification
Course content for the University of Bristol Design Verification course.