tanbour's repositories

CNN_VGG19_verilog

Convolution Neural Network of vgg19 model in verilog

Language:VerilogStargazers:0Issues:0Issues:0

usbcorev

A full-speed device-side USB peripheral core written in Verilog.

Language:VerilogLicense:NOASSERTIONStargazers:0Issues:0Issues:0

openofdm

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

x393_sata

mirror of https://git.elphel.com/Elphel/x393_sata

Language:VerilogLicense:GPL-3.0Stargazers:0Issues:0Issues:0

FPGAePWM_CP

C28x compatible implementation of an ePWM module on FPGA

Stargazers:0Issues:0Issues:0

nvdla.github.io

NVDLA Web Content

Language:HTMLLicense:NOASSERTIONStargazers:0Issues:0Issues:0

doc

Documentation for NVDLA.

Language:HTMLLicense:NOASSERTIONStargazers:0Issues:0Issues:0

hw

RTL, Cmodel, and testbench for NVDLA

Language:VerilogLicense:NOASSERTIONStargazers:0Issues:0Issues:0

eddr3

mirror of https://git.elphel.com/Elphel/eddr3

Language:VerilogStargazers:0Issues:0Issues:0

Convolutional-Neural-Network

Implementation of CNN using Verilog

Language:VerilogStargazers:0Issues:0Issues:0

miaow

An open source GPU based off of the AMD Southern Islands ISA.

Language:VerilogLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

riscv-soc-book

关于RISC-V你所需要知道的一切

Stargazers:0Issues:0Issues:0

verilog-sid-mos6581

MOS6581 SID chip emulator in SystemVerilog

Language:SystemVerilogStargazers:0Issues:0Issues:0
Language:VerilogStargazers:0Issues:0Issues:0

Hardware-CNN

A convolutional neural network implemented in hardware (verilog)

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

mipi_mphy

Specification for mipi-M-PHY

Language:SystemVerilogStargazers:1Issues:0Issues:0

SystemVerilogReference

training labs and examples

Language:SystemVerilogStargazers:0Issues:0Issues:0

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Language:VerilogLicense:NOASSERTIONStargazers:0Issues:0Issues:0

SDRAM-Controller

EDEC STANDARD Double Data Rate (DDR) SDRAM Specification

Language:SystemVerilogStargazers:1Issues:0Issues:0

CPU_design

Verilog of a tapeout reprogrammable chip for analog circuit auto-tuning

Language:CoqStargazers:0Issues:0Issues:0

cs231n-project

CNN accelerator

Language:TclLicense:MITStargazers:0Issues:0Issues:0

verilog-lfsr

Fully parametrizable combinatorial parallel LFSR/CRC module

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

verilog-i2c

Verilog I2C

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0
Language:SystemVerilogStargazers:1Issues:0Issues:0

EPC-Gen2-RFID-Tag-Baseband-Processor

Verilog library of EPC Gen-2 RFID Tag Baseband Processor for IC and FPGA designers

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

AMBA_AXI3

System Verilog and Emulation. Written all the five channels.

Language:SystemVerilogLicense:NOASSERTIONStargazers:0Issues:0Issues:0

SystemVerilog

Мой учебный репозиторий для проектов на SystemVerilog в среде Quartus

Language:SystemVerilogStargazers:0Issues:0Issues:0

4-way-set-associative-cache-verilog

Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy

Language:VerilogStargazers:0Issues:0Issues:0

verilog-cam

Verilog Content Addressable Memory Module

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

dvi_lvds

DVI to LVDS Verilog converter

Language:VerilogStargazers:0Issues:0Issues:0