tanbour's repositories
CNN_VGG19_verilog
Convolution Neural Network of vgg19 model in verilog
usbcorev
A full-speed device-side USB peripheral core written in Verilog.
openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
x393_sata
mirror of https://git.elphel.com/Elphel/x393_sata
FPGAePWM_CP
C28x compatible implementation of an ePWM module on FPGA
nvdla.github.io
NVDLA Web Content
doc
Documentation for NVDLA.
hw
RTL, Cmodel, and testbench for NVDLA
eddr3
mirror of https://git.elphel.com/Elphel/eddr3
Convolutional-Neural-Network
Implementation of CNN using Verilog
miaow
An open source GPU based off of the AMD Southern Islands ISA.
riscv-soc-book
关于RISC-V你所需要知道的一切
verilog-sid-mos6581
MOS6581 SID chip emulator in SystemVerilog
Hardware-CNN
A convolutional neural network implemented in hardware (verilog)
SystemVerilogReference
training labs and examples
ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
SDRAM-Controller
EDEC STANDARD Double Data Rate (DDR) SDRAM Specification
CPU_design
Verilog of a tapeout reprogrammable chip for analog circuit auto-tuning
cs231n-project
CNN accelerator
verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
verilog-i2c
Verilog I2C
EPC-Gen2-RFID-Tag-Baseband-Processor
Verilog library of EPC Gen-2 RFID Tag Baseband Processor for IC and FPGA designers
AMBA_AXI3
System Verilog and Emulation. Written all the five channels.
SystemVerilog
Мой учебный репозиторий для проектов на SystemVerilog в среде Quartus
4-way-set-associative-cache-verilog
Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
verilog-cam
Verilog Content Addressable Memory Module
dvi_lvds
DVI to LVDS Verilog converter