tanbour's repositories
fpga-hash-table
Simple hash table on Verilog (SystemVerilog)
bch_verilog
Verilog based BCH encoder/decoder
566_project
Source repository for 566 class project
verilog-dsp
Verilog digital signal processing components
nysa-sdio-device
SDIO Device Verilog Core
sort
排序 verilog 实现
CAN-Bus-Controller
An CAN bus Controller implemented in Verilog
NeoGeoHDMI
Verilog project that takes the digital video and audio from a Neo Geo MVS before going through the DACs and outputs the signals over HDMI
system-verilog-patterns
SystemVerilog Design Patterns
verilog-arbiter
A look ahead, round-robing parametrized arbiter written in Verilog.
gplgpu
GPL v3 2D/3D graphics engine in verilog
jpegencode
JPEG Encoder Verilog
NCSU-Low-Power-RFID
Verilog code for a low power RFID chip that will communicate with I2C sensors.
cordic
An implementation of the CORDIC algorithm in Verilog.
SIFT-implementation-in-Verilog
Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations
Verilog-MIPSProcessor
Full implementation of a modifed MIPS processor in Verilog.
sveditor-ref-designs
Reference designs for use in SVEditor benchmarking
Atalanta
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
rfid-verilog
RFID tag and tester in Verilog
cachesim
Cache system simulator for C++ and Verilog VPI.
4way-cache
Verilog cache implementation of 4-way FIFO 16k Cache
airblue_7dec12
airblue: trying to simulate the noisy channel and am getting "undefined symbol: gsl_rng_default" error
doxverilog
Eric's branch of Doxverilog (doxygen + doxverilog patch)
md5_core
MD5 core in verilog
DDR2_Controller
DDR2 memory controller written in Verilog
netv_fpga_hdmi_overlay
Mirror of NeTV FPGA Verilog Code
verilog-sha256
Implementation of the SHA256 Algorithm in Verilog