tanbour's repositories
Formal_Verification
Coverage Closure and Bug Hunt Project
antikernel
The Antikernel operating system project
antikernel-ipcores
FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
chisel3
Chisel 3
cocotb
Coroutine Co-simulation Test Bench
cores
Various HDL (Verilog) IP Cores
Design-Verification
Course content for the University of Bristol Design Verification course.
Exploring-Zynq-MPSoC-CN
Exploring Zynq ® MPSoC Chinese
firrtl
Flexible Intermediate Representation for RTL
FPGA-FOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
fpga_pio
An attempt to recreate the RP2040 PIO in an FPGA
Functional-Safety-Notes
基于Xilinx平台的功能安全笔记
QSPI_FOR_SOC
QSPI for SoC
qspiflash
A set of Wishbone Controlled SPI Flash Controllers
rggen-verilog
Verilog writer plugin for RgGen
scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
swerv_sim
simulation env for swerv_th1, which is base on vcs & verdi
UART_VLC_Transmission
UART (9600/115200) to VLC (RS code/Manchester code/8x Sampling Syncronization)
wtfpython-cn
wtfpython的中文翻译/施工结束/ 能力有限，欢迎帮我改进翻译
wujian100_open
IC design and development should be faster，simpler and more reliable