tanbour's repositories
wtfpython-cn
wtfpython的中文翻译/施工结束/ 能力有限，欢迎帮我改进翻译
wtfpython
A collection of surprising Python snippets and lesser-known features.
rocket-chip
Rocket Chip Generator
Python-100-Days
Python - 100天从新手到大师
Tool-Make-Script
Synopsys Design compiler, VCS and Tetra-MAX
Tri-Mode-Ethernet-MAC-10-100-1000-
Ethernet-MAC System verilog
verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
hdl
HDL libraries and projects
e200_opensource
The Ultra-Low Power RISC Core
veriloggen
Veriloggen: A library for constructing a Verilog HDL source code in Python
SV-for-Design
Systemverilog Design Packages
verilog-math
Mathematical Functions in Verilog
DV_S2QED_RISCV
Verification of RISC-V Processor Core(s) using S2QED. some formal code
Learning-NVDLA-Notes
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit.
sha512
Verilog implementation of the SHA-512 hash function.
sha1
Verilog implementation of the SHA-1 cryptgraphic hash function
NyuziProcessor
GPGPU microprocessor architecture
mor1kx
mor1kx - an OpenRISC 1000 processor IP core
SYMPL-GP-GPU-Compute-Engines
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
moneroasic
Cryptonight Monero Verilog code for ASIC
Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
verilog-ethernet
Verilog Ethernet components
verilog-axis
Verilog AXI stream components
oh
Silicon proven Verilog library for IC and FPGA designers
Scipio
A RISC-V CPU implemented in Verilog
RISCV_CPU
A RISCV_CPU written in verilog