rggen / rggen

Code generation tool for control and status registers

rggen/rggen Issues

Parameterized bit field with
Updated 2 months ago
Veryl support
Updated 2 months ago
rc, w0c, w1c, wc, woc: bit field set when it should be cleared?
Closed 2 months ago3
[Request] Add support for library name
Closed 3 months ago15
[VHDL] Type mismatch error for an array register with offset address 0x0
Closed 3 months ago1
[VHDL] Array port
Updated 3 months ago
Specify reset domain
Updated 3 months ago
backdoor read has no side effect
Closed 3 months ago1
Implement: Parameter-Driven Bit width assignment in SV/Verilog files from input file formats
Closed 3 months ago4
Drop XLS support
Closed 4 months ago
Cannot load ODS file including multi-line cell correctly
Closed 4 months ago
Redefine rws bit field type
Closed 4 months ago
Change loader priority
Closed 4 months ago
Update copyright year
Closed 4 months ago
YAML specification for custom bit type does not seem to match documentation
Closed 4 months ago1
Generate IP-XACT
Updated 4 months ago
Update option description
Closed 4 months ago1
Update spreadbase gem
Closed 4 months ago
Stop using sonarcloud
Closed 5 months ago
Add Ruby 3.3 support and drop Ruby 2.7 support
Closed 5 months ago
REGISTER_INDEX
Closed 5 months ago2
Add method to check if the given component is defined
Closed 5 months ago
Modify existing features
Closed 5 months ago
Update development gems
Closed 5 months ago
Error while starting the uvm_reg_mem_hdl_paths_seq.
Closed 6 months ago4
Cannot load default plugins when newer RgGen is installed
Closed 7 months ago1
Support SPI as bus interface
Updated 7 months ago7
Provide Python bindings
Updated 7 months ago1
Add RW register type
Closed 8 months ago
separating HW and SW access
Closed 8 months ago2
Change protocol definition of rggen_register_if
Closed 8 months ago
Add 'strobe_width' field
Closed 8 months ago1
Refer configuration object from InputData object for RegisterMap
Closed 8 months ago
Add W1S/W1C access types
Closed 8 months ago1
block_0.xlsx can't change register name
Closed 9 months ago2
Vivado Doesn't like this systemverilog code
Closed 9 months ago6
Typo
Closed 9 months ago
Check reserved words
Updated 10 months ago1
SVD support
Updated a year ago1
Create Docker image
Closed a year ago1
Compile error when backdoor access is not enabled
Closed a year ago
Fix warnings reported by Verilator
Closed a year ago3
Constants and expressions support
Closed a year ago3
Enumeration types support
Closed a year ago5
Interrupt support
Closed a year ago1
Addressing mode support
Closed a year ago1
External memory support
Closed a year ago1
Add 'INSERT_SLICER' paraemter to generated RTL modules
Closed a year ago
step optiton for size feature
Closed a year ago
input value conversion is invoked for nil value
Closed a year ago1