Code generation tool for control and status registers
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taichi-ishitani opened this issue 10 months ago · comments
https://github.com/rggen/rggen-systemverilog/blob/4d046630203b14881e43b1ea5e330c85332ce7c6/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb#L8
eigher -> either