Fix warnings reported by Verilator
taichi-ishitani opened this issue · comments
Verilator reports following warnings. Fix them.
SystemVerilog RTL
%Warning-WIDTH: rtl/apb/block_0.sv:167:37: Operator AND expects 32 bits on the RHS, but RHS's CONST '1'h1' generates 1 bits.
: ... In instance top.u_block_0
167 | if (!(((32'h0001ffff) >> __i) & 1'b1)) begin : g
| ^
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_default_register.sv:5:37: Operator VAR 'OFFSET_ADDRESS' expects 8 bits on the Initial value, but Initial value's CONST '32'h30' generates 32 bits.
: ... In instance top.u_block_0.g_register_10.g[0].u_register
5 | parameter bit [ADDRESS_WIDTH-1:0] OFFSET_ADDRESS = '0,
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_register_common.sv:57:57: Operator SUB expects 32 bits on the LHS, but LHS's FUNCREF 'calc_start_address' generates 8 bits.
: ... In instance top.u_block_0.g_register_0.u_register.u_register_common
57 | return ADDRESS_WIDTH'(calc_start_address(index + 1) - 1);
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_or_reducer.sv:20:27: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'half_n' generates 32 bits.
: ... In instance top.u_block_0.u_adapter.u_adapter_common.u_mux.g.u_reducer
20 | list[list_index] = half_n;
| ^
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_or_reducer.sv:26:27: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'current_n' generates 32 bits.
: ... In instance top.u_block_0.u_adapter.u_adapter_common.u_mux.g.u_reducer
26 | list[list_index] = current_n;
| ^
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_or_reducer.sv:29:19: Operator SUB expects 32 bits on the RHS, but RHS's SEL generates 16 bits.
: ... In instance top.u_block_0.u_adapter.u_adapter_common.u_mux.g.u_reducer
29 | current_n -= list[list_index];
| ^~
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_adapter_common.sv:50:51: Operator ADD expects 32 bits on the LHS, but LHS's VARREF 'BASE_ADDRESS' generates 16 bits.
: ... In instance top.u_block_0.u_adapter.u_adapter_common
50 | end_address = ADDRESS_WIDTH'(BASE_ADDRESS + BYTE_SIZE - 1);
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_register_common.sv:114:33: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARXREF 'value' generates 32 bits.
: ... In instance top.u_block_0.g_register_0.u_register.u_register_common
114 | assign register_if.value = bit_field_if.value;
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_apb_adapter.sv:24:29: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's VARXREF 'paddr' generates 16 bits.
: ... In instance top.u_block_1.u_adapter
24 | assign bus_if.address = apb_if.paddr;
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_external_register.sv:74:33: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARXREF 'read_data' generates 32 bits.
: ... In instance top.u_block_0.g_register_15.u_register
74 | assign register_if.value = bus_if.read_data;
|
%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_apb_bridge.sv:14:27: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS's VARXREF 'address' generates 8 bits.
: ... In instance top.u_bridge
14 | assign apb_if.paddr = bus_if.address;
| ^
%Warning-CMPCONST: /work/rtl/rggen-sv-rtl/rggen_address_decoder.sv:27:33: Comparison is constant due to limited range
: ... In instance top.u_block_0.g_register_15.u_register.u_decoder
27 | (i_address[WIDTH-1:LSB] <= END_ADDRESS[WIDTH-1:LSB] )
| ^~
Verilog RTL
%Warning-WIDTH: rtl/apb/block_0.v:192:33: Operator AND expects 32 bits on the RHS, but RHS's CONST '1'h1' generates 1 bits.
: ... In instance block_0
192 | if (!((32'h0001ffff >> __i) & 1'b1)) begin : g
%Warning-WIDTH: rtl/apb/block_0.v:2130:59: Operator AND expects 8 bits on the RHS, but RHS's REPLICATE generates 2 bits.
: ... In instance block_0
2130 | (((REGISTER_10_BIT_FIELD_1_INITIAL_VALUE) >> ((2) * (j))) & {(2){1'b1}})),
| ^
%Warning-WIDTH: /work/rtl/rggen-verilog-rtl/rggen_default_register.v:5:33: Operator VAR 'OFFSET_ADDRESS' expects 8 bits on the Initial value, but Initial value's CONST '32'h30' generates 32 bits.
: ... In instance block_0.g_register_10.g[0].u_register
5 | parameter [ADDRESS_WIDTH-1:0] OFFSET_ADDRESS = {ADDRESS_WIDTH{1'b0}},
| ^~~~~~~~~~~~~~
%Warning-WIDTH: /work/rtl/rggen-verilog-rtl/rggen_bit_field.v:4:25: Operator VAR 'INITIAL_VALUE' expects 2 bits on the Initial value, but Initial value's CONST '8'h0' generates 8 bits.
: ... In instance block_0.g_register_10.g[0].g_bit_field_1.g[0].u_bit_field
4 | parameter [WIDTH-1:0] INITIAL_VALUE = {WIDTH{1'b0}},
| ^~~~~~~~~~~~~
%Warning-WIDTH: /work/rtl/rggen-verilog-rtl/rggen_register_common.v:59:42: Operator ADD expects 32 bits on the LHS, but LHS's VARREF 'OFFSET_ADDRESS' generates 8 bits.
: ... In instance block_0.g_register_0.u_register.u_register_common
59 | calc_start_address = OFFSET_ADDRESS + BUS_BYTE_WIDTH * index;
|
%Warning-WIDTH: /work/rtl/rggen-verilog-rtl/rggen_or_reducer.v:77:41: Operator FUNCREF 'get_sub_n_list' expects 16 bits on the Function Argument, but Function Argument's VARREF 'N' generates 32 bits.
: ... In instance block_0.g_register_6.u_register.u_register_common.u_read_data_mux.g.u_reducer
77 | localparam [16*N-1:0] SUB_N_LIST = get_sub_n_list(N);
| ^~~~~~~~~~~~~~
%Warning-WIDTH: /work/rtl/rggen-verilog-rtl/rggen_adapter_common.v:67:19: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 9 bits.
: ... In instance rggen_axi4lite_adapter.u_adapter_common
67 | end_address = BASE_ADDRESS + BYTE_SIZE - 1;
|
%Warning-CMPCONST: /work/rtl/rggen-verilog-rtl/rggen_address_decoder.v:49:31: Comparison is constant due to limited range
: ... In instance block_0.g_register_15.u_register.u_decoder
49 | (address[WIDTH-1:LSB] <= END_ADDRESS[WIDTH-1:LSB] );
| ^~
%Warning-UNSIGNED: /work/rtl/rggen-verilog-rtl/rggen_address_decoder.v:48:31: Comparison is constant due to unsigned arithmetic
: ... In instance block_0.g_register_0.u_register.u_register_common.g_decoder[0].u_decoder
48 | (address[WIDTH-1:LSB] >= START_ADDRESS[WIDTH-1:LSB]) &&
| ^~
%Warning-UNOPTFLAT: rtl/apb/block_0.v:150:17: Signal unoptimizable: Feedback to clock or circular logic: 'block_0.w_register_value'
150 | wire [1599:0] w_register_value;
| ^~~~~~~~~~~~~~~~
rtl/apb/block_0.v:150:17: Example path: block_0.w_register_value
rtl/apb/block_0.v:860:10: Example path: ASSIGNW
rtl/apb/block_0.v:760:17: Example path: block_0.g_register_4.w_bit_field_value
rtl/apb/block_0.v:781:8: Example path: ASSIGNW
rtl/apb/block_0.v:150:17: Example path: block_0.w_register_value
%Warning-WIDTH: rtl/apb/block_0.sv:167:37: Operator AND expects 32 bits on the RHS, but RHS's CONST > '1'h1' generates 1 bits. : ... In instance top.u_block_0 167 | if (!(((32'h0001ffff) >> __i) & 1'b1)) begin : g |
To resolve this warning, change the macro definition like below.
`ifndef rggen_tie_off_unused_signals
`define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
if (1) begin : __g_tie_off \
genvar __i; \
for (__i = 0;__i < WIDTH;++__i) begin : g \
if ((((VALID_BITS) >> __i) % 2) == 1)begin : g \
assign RIF.read_data[__i] = 1'b0; \
assign RIF.value[__i] = 1'b0; \
end \
end \
end
`endif%Warning-WIDTH: /work/rtl/rggen-sv-rtl/rggen_default_register.sv:5:37: Operator VAR 'OFFSET_ADDRESS' > expects 8 bits on the Initial value, but Initial value's CONST '32'h30' generates 32 bits. : ... In instance > top.u_block_0.g_register_10.g[0].u_register 5 | parameter bit [ADDRESS_WIDTH-1:0] OFFSET_ADDRESS = '0,
This warning is caused by an offset address calucuration like this.
https://github.com/rggen/rggen-sample/blob/42fa8f6f6cf0c56dedc2a377693ac76151794ec0/block_0.sv#L1731
To fix the warning, insert a width cast to elements of calucration like below.
8'h30+8'(8*i)%Warning-UNOPTFLAT: rtl/apb/block_0.v:150:17: Signal unoptimizable: Feedback to clock or circular > logic: 'block_0.w_register_value' 150 | wire [1599:0] w_register_value; | ^~~~~~~~~~~~~~~~ rtl/apb/block_0.v:150:17: Example path: block_0.w_register_value rtl/apb/block_0.v:860:10: Example path: ASSIGNW rtl/apb/block_0.v:760:17: Example path: > block_0.g_register_4.w_bit_field_value rtl/apb/block_0.v:781:8: Example path: ASSIGNW rtl/apb/block_0.v:150:17: Example path: block_0.w_register_value
It's difficult to fix this warning so -Wno-unoptflat switch is needed.