Check reserved words

[Taichi Ishitani]

Report an error when a SV/Verilog/VHDL reserved words is specified as a register block/register file/register/bit field name.
This is to avoid a compile error when loading a generated source file.

[Taichi Ishitani]

Lise of VHDL reserved workds
https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/VHDL-RESERVED-Words