lcapossio

openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

litex

Build your hardware, easily!

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

altium-library

Open source Altium Database Library with over 200,000 high quality components and full 3d models.

openocd

Official OpenOCD Read-Only Mirror (no pull requests)

clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

serv

SERV - The SErial RISC-V CPU

linux-xlnx

The official Linux kernel from Xilinx

bsc

Bluespec Compiler (BSC)

embeddedsw

Xilinx Embedded Software (embeddedsw) Development

verilog-axis

Verilog AXI stream components for FPGA implementation

microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

litedram

Small footprint and configurable DRAM core

pyuvm

The UVM written in Python

rggen

Code generation tool for control and status registers

RapidWright

Build Customized FPGA Implementations for Vivado

hardh264

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

Serial-Oscilloscope

OpenFASOC

Fully Open Source FASOC generators built on top of open-source EDA tools

OSVVM

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Toooba

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

verilog-cam

Verilog Content Addressable Memory Module

fsva

FuseSoc Verification Automation

Masking-Detection

Object Detection About Masking For Xilinx Summer School

WAVE-Vivado

HDL and C source for WAVE Zynq Ultrascale+ SoC

betrusted-hardware-xt

Early experimental circuits for the betrusted hardware design

acceleration_firmware_ultra96v2

Avnet ultra96v2 firmware. Package for enabling hardware acceleration capabilities in ROS 2 with Ultra96v2 board.

resume