PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

PyHDI/Pyverilog Issues

ANSI Style localparam causes parsing error
Updated a month ago
AST node
Updated 5 months ago1
TypeError: generate() got an unexpected keyword argument 'reorder'
Updated 7 months ago2
About control flow analysis
Updated 8 months ago
Parse Error: Cannot parse a function
Updated 9 months ago2
Codegen arrays
Updated 9 months ago
Unsized numbers without base solution
Updated 9 months ago
Unsized numbers without base not supported
Updated 9 months ago2
parser error
Updated 9 months ago
Attribute error in parser
Updated 9 months ago
Preprocessing Issue when included file is in different directory
Closed 10 months ago1
Can not support "generate case" statement
Updated a year ago
unsufficient parse for large scale verilog design
Updated a year ago
Specify statements
Updated a year ago
Can it work on hierarchy of design?
Updated 2 years ago2
Error running example_graphgen.py
Updated 2 years ago1
Parsing Issues
Updated 2 years ago1
ParseError for User Defined Primitives
Updated 2 years ago1
Parser Error for resettable D Flip-Flop
Updated 2 years ago1
Parse Error for Inverter Gate
Updated 2 years ago
function in module can not be parse, and get error
Updated 2 years ago13
Parsing Error for integer memories
Updated 2 years ago
TypeError: generate() got an unexpected keyword argument 'reorder'
Updated 2 years ago2
dataflow analysis error
Updated 2 years ago1
Extracting design information via API
Updated 2 years ago
How to setup and install pyverilog inside py virtual environment?
Closed 2 years ago1
windows error -run example_parser.py
Closed 2 years ago1
A bug when parsing nesting ifStatement
Updated 2 years ago
Functions with port lists can't be parsed
Updated 2 years ago
error
Updated 3 years ago
Modify AST generated by PyVerilog
Updated 3 years ago
How to append new assign to a module from verilog code?
Updated 3 years ago
how
Updated 3 years ago
isWireArray(termtype) is missing in /utils/signaltype.py
Updated 3 years ago1
gate level netlist to rtl
Updated 3 years ago
ast.IntConst creates collisions on dicts
Updated 3 years ago2
OSError: Format: "dot" not recognized. Use one of:
Updated 3 years ago
SVA assert / assume/ cover property support
Updated 3 years ago1
The verilog parser doesn't support the dot operator in the module header
Updated 3 years ago1
Delays incorrectly printed on output to verilog
Updated 3 years ago1
question regarding implementation
Closed 3 years ago1
Not able to run
Updated 3 years ago
vparser/parser.py mkdir arguement error
Closed 3 years ago1
File not found error
Updated 4 years ago
Sample code for feature extraction from verlog file
Updated 4 years ago
Assignment with strength does not compile
Updated 4 years ago
Supporting function calls in parameter/localparam value definitions by dataflow.signalvisitor
Updated 4 years ago
Module Initiation Syntax
Closed 4 years ago
New release with latest ply
Closed 4 years ago3
Dataflow graphgen has a namespace problem that causes error when using reorder option
Closed 4 years ago3