Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado

http://www.rapidwright.io

Xilinx/RapidWright Issues

Query on function arguments
Updated 14 days ago3
Running Rapidwright jython through script and eclipse setup issue
Updated a month ago2
How to convert the intermediate result of vpr into a dcp file?
Updated a month ago3
Discrepancy between RapidWright's pblock.getAllSites with Vivado TCL
Closed a month ago1
Alveo U250 DSP48E2_{X28|X29} cell: <LOCKED>(BEL: (unplaced))
Closed a month ago2
xcvh1782 wire/node mismatch
Updated 2 months ago5
make blackblox issue
Updated 3 months ago9
Can't generate DeviceResources file for Versal
Updated 3 months ago1
make multiple black boxes
Closed 3 months ago1
`design.getBELAttrs()` returns None
Closed 3 months ago3
Vivado not preserving the placement of DSP48E2 and RAMB18E2 cells
Closed 3 months ago8
All zero values in frames of placed cells
Closed 3 months ago1
No possible Unisim of VCC and GND for 7-series FPGAs
Closed 3 months ago3
It's better for `netlist.getTopCellInst().getPortInsts()` to not return empty list.
Updated 3 months ago2
Odd behavior with Wire constructor and Node.isInvalidNode
Closed 4 months ago2
pip.getEndNode returning null
Closed 4 months ago2
Install instructions should not recommend vulnerable libpng libraries
Updated 4 months ago1
Unable to use rapidwright.bitstream APIs on python
Closed 5 months ago6
GlobalSignalRouting.getLCBPinMappings() fails for some pins
Updated 5 months ago
[Versal BELAttr] Parsing issue
Closed 5 months ago6
ROCm Crossfire Integration
Updated 5 months ago3
xdl2dcp
Closed 6 months ago2
LUTTools.swapSingleLutPins() cannot swap H[1-6] when used as WA
Updated 6 months ago
Minor Javadoc issues with tags
Closed 6 months ago
How to use outmuxa?
Closed 7 months ago4
Merging designs with naming collision encrypted cells
Closed 7 months ago3
Generate dcp through custom define file
Closed 7 months ago8
API to use vivado?
Closed 7 months ago2
getByteOffset method in Frame class
Updated 7 months ago3
TimingAndWirelengthReport.main() has an error
Closed 7 months ago1
FPGAIF physical net includes BEL pin that is not connected to net
Closed 7 months ago1
DREAMPlaceFPGA tutorial missing the step to generate the device IF file
Closed 7 months ago9
Device data generate
Closed 8 months ago4
[WARNING: Hierarchy information reference to non-existent net XXX] Using ModuleInst
Closed 8 months ago6
Encrypted cell placement
Closed 8 months ago4
RW links net to the wrong port in RAM32M DI* bus signal
Closed 8 months ago7
NullPointerException at edif.EDIFHierPortInst.getPhysicalCell
Closed 8 months ago2
can't read "io_pin_sites": no such variable @ 030-iob18 fuzzer
Closed 9 months ago2
Interchange writer misses belPin
Closed 9 months ago7
Design.routeSites() unable to route Carry8 DI0 to site pin.
Updated 10 months ago
Pin map conflicts with a LUT5-LUT6 pair.
Closed 10 months ago1
RW reports CLK_INVERTED as 1'b1 when it is reported as 1'b0 in Vivado
Closed 10 months ago1
RWRoute fails with null pointer exception on placement produced with nextpnr
Closed 10 months ago1
Problem with Cell.getCompatiblePlacements() - hdi_primitives library not recognized as part of design netlist
Closed a year ago8
RWRoute only assigns a single SitePinInst to the ground net.
Closed a year ago3
Failed to reliably download file
Closed a year ago7
[Maven] rapidwright as Maven dependency fails
Closed a year ago5
[Interchange] EnumerateCellBelMapping Speedup Opportunity
Updated a year ago
[ABCD]OUTMUX not always showing up in siteInst.getUsedSitePIPs()
Closed a year ago5
distinguishing const0 driven by LUT
Closed a year ago3