hutch31

gpt-engineer

Specify what you want it to build, the AI asks for clarification, and then builds it.

steam-for-linux

Issue tracking for the Steam for Linux beta client

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

verilog-ethernet

Verilog Ethernet components for FPGA implementation

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

migen

A Python toolbox for building complex digital hardware

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

protocol

An ASCII Header Generator for Network Protocols

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

chisel2-deprecated

tiny-ECDH-c

Small portable Elliptic-Curve Diffie-Hellman in C

sv2chisel

(System)Verilog to Chisel translator

eve-wspace

Wormhole mapping and corporation management for Eve Online.

System-Verilog-Packet-Library

System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers

ip-contributions

For contributions of Chisel IP to the chisel community.

nfmac10g

Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC

fwrisc

Featherweight RISC-V implementation

verilog-utils

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

tv80

TV80 Z80-compatible microprocessor

proton

gsn2x

Tool to create graphical representations of Goal Structuring Notations from YAML.

chisel-aes

Chisel implementation of AES

easysoc-diagrammer

Layout, rendering ELK Graph generated by easysoc-firrtl, and display the graph as an interactive diagram to represent Chisel generated Firrtl circuits.

sdlib

srdy-drdy library

trivium

different implementations of the trivium stream-cipher

c2verilog

Inofficial version of c-to-verilog.com

vpi_pcap_dump

Dump packets from Verilog to a pcap file using VPI calls from simulator

ansible-playbooks

Playbooks for configuring CIC Workstations and Servers

MACsec-Test-Vectors

microecc