Giters
YosysHQ
/
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
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2956
Watchers:
165
Issues:
176
Forks:
736
YosysHQ/picorv32 Issues
Building code with riscvRV32imc toolchain the execution is stucking
Updated
a month ago
how to access picorv32_pcpi_mul from software?
Updated
a month ago
Comments count
1
how to run dhrystone benchmark
Updated
2 months ago
Dhrystone Floating Extension Problem ?
Updated
2 months ago
Verilog HDL Module Instantiation error at hx8kdemo.v(65)
Updated
3 months ago
Comments count
1
yices?
Closed
3 months ago
Comments count
2
rdcycle RISC-V instruction giving too high number of clock cycles
Closed
3 months ago
Comments count
2
Issue with branch while using BRAM.
Updated
3 months ago
Comments count
1
Executing cxxdemo with verilator causing memory out of bound problem:
Updated
4 months ago
-nostdlib removal and memory size in simulation
Closed
4 months ago
Comments count
1
Bug when using RV32E (ENABLE_REGS_16_31=0)
Closed
4 months ago
Bug: TRAP after >8000 clock cycles
Closed
4 months ago
Comments count
7
Executing C code for PQC in PicoRV32 and verilator, openSSL/config.h not found
Closed
4 months ago
Comments count
3
Building a RV32I Toolchain: undefined reference to `_initialize_string_view_selftests()'
Updated
8 months ago
Comments count
6
Bug report: fence instruction raises instruction trap
Closed
8 months ago
Is this project still maintained?
Updated
8 months ago
Running new Assembly Code on PicoRV32
Updated
8 months ago
Comments count
1
wbm_sel_o == 0 during read transactions
Updated
10 months ago
JAL instruction not working as expected
Updated
10 months ago
Why it doesn't has memory module in picoRV code? Why in the testench?
Updated
a year ago
What is PCPI base address?
Closed
a year ago
Comments count
5
Building a pure RV32I Toolchain
Updated
a year ago
[Bug report] Wrong performance counter address
Updated
a year ago
[Bug report] Performance counters reads are incorrectly required to be of csrrs opcode
Updated
a year ago
[Bug report] Performance counters are not writable
Updated
a year ago
[Bug report] Some mandatory CSRs are not implemented
Updated
a year ago
[Bug report] Attempt to access a non-implemented CSR should raise an illegal instruction
Updated
a year ago
Trap in simulation with existing compiler
Closed
a year ago
Comments count
7
Dynamically Setting PROGADDR_RESET
Closed
a year ago
Comments count
1
read delay of PICORV32_REGS must be 0?
Updated
a year ago
Comments count
1
calling custom IRQ instructions in C code
Updated
a year ago
ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.
Updated
2 years ago
Trace encoder
Closed
2 years ago
picorv32_waitirq_insn
Updated
2 years ago
Comments count
2
Toolchain: would it make sens to move to gcc-riscv64-unknown-elf and friends only?
Updated
2 years ago
Comments count
2
RISCV32I
Updated
2 years ago
hardware trap for RV32E
Updated
2 years ago
Unable to build GCC
Closed
2 years ago
Comments count
1
Q) How to fetch & decode compressed instructions
Updated
2 years ago
can picorv32 run on iCE40UP5k
Closed
3 years ago
Comments count
2
Support for Synchronous Reads for Register File
Updated
3 years ago
Linux Compatibility
Updated
3 years ago
Comments count
1
makehex.py for compressed instructions
Updated
3 years ago
could I use Murax of VexRiscv + picorv32 firmware
Updated
3 years ago
Comments count
1
Issue with Trap under vivado scripts
Updated
3 years ago
Beginner Question : Why I can't run the Makefile?
Closed
3 years ago
Comments count
1
Beginner Question : Flow of the execution of this whole code in Xilinx ISE?
Updated
3 years ago
make test fails due to -lgcc
Closed
3 years ago
Comments count
1
problem during the build tools
Closed
3 years ago
How is the length of the storage area calculated?
Updated
3 years ago
Comments count
2
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