m-labs / migen

A Python toolbox for building complex digital hardware

https://m-labs.hk/migen

m-labs/migen Issues

Subvector of Cat() incorrect assignment
Closed a year ago1
`else` branch elided in generated Verilog
Updated a year ago3
Conda installation fails
Closed 5 years ago10
Better FMC support
Updated 2 years ago1
tests fail when building with Python 3.11
Closed 2 years ago4
[Sim] Error with fsm delayed_enter method
Updated 2 years ago
Invalid synthesis output for TSTriple width > 1 (Vivado)
Closed 2 years ago1
Problem with an instance
Closed 2 years ago1
Problem with copy_sources(self, build_dir, subdir="imports")
Updated 2 years ago7
move the conditional part of `toolchain.build(run=True/False)` to a separate method
Updated 2 years ago1
Insert a `define in the top scope
Closed 2 years ago1
Incorrect simulation of Cat()
Updated 2 years ago3
Unable to build gateware for Kasli v2.0
Closed 2 years ago1
Instance parameter value needlessly translated to narrowed width causes errors
Closed 3 years ago5
data change issue inside FSM state
Closed 3 years ago
Signal Names of FSM
Updated 3 years ago
TSTriple() usage
Updated 3 years ago
ClockDomain "helper" used for I2C master
Closed 3 years ago
How to create a ClockDomain for I2C ?
Closed 3 years ago1
how to put more than one statement in each case value ?
Closed 3 years ago
question
Closed 3 years ago
FSM() always reset the fields being modified in the beginning of the loop
Closed 3 years ago2
Cycle accurate simulation
Updated 3 years ago2
review kasli_soc pinout
Closed 3 years ago4
Add example for a design that runs on a board, e.g. red pitaya
Closed 4 years ago2
How to convert migen source code into to Verilog?
Closed 4 years ago2
Migen - Cat() simulation not matching verilog when Cat_object is sliced
Updated 4 years ago8
Possibly incorrect VCD file generated
Closed 4 years ago1
Question: How to write tests and convert higher-level modules with other modules
Closed 4 years ago3
python dependency wheel missing
Updated 4 years ago
bitwise invert of unsigned int is negative
Closed 4 years ago4
SyncFIFO self.writable signal is one cycle delayed
Closed 4 years ago1
SyntaxWarning in migen\migen\fhdl\visit.py
Closed 5 years ago
Add more comments to examples
Updated 5 years ago1
please add install instruction to readme?
Closed 5 years ago4
Limited object scope of eq operator causing multiple conflicting drivers
Closed 5 years ago1
IOBuf inference only generate first bit of vector
Closed 5 years ago4
[migen][sim] How to import verilog source into migen design file ?
Updated 5 years ago1
Reduction operators
Closed 5 years ago2
<< seems buggy
Updated 5 years ago2
First class unit test support
Closed 5 years ago4
.part() is converted to Verilog that can evaluate to 'x
Updated 5 years ago1
Finalization is order-dependent, leading to footguns
Updated 5 years ago1
Unable to have two blocks with "always @(posedge mem_clk) begin"
Closed 5 years ago7
Create experimental migen using edalize as part of migen.build
Closed 5 years ago8
set LC_ALL environment variable to "C" before running Vivado
Closed 5 years ago
`collections` is deprecated in python 3.7
Closed 5 years ago3
No module named 'migen.fhdl.std'
Closed 6 years ago4
Help with design low-level HDL language
Closed 6 years ago8
SyncFIFO replace signal not ASIC compatible
Closed 6 years ago6