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ucb-bar
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chisel2-deprecated
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chisel.eecs.berkeley.edu
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388
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92
Issues:
326
Forks:
90
ucb-bar/chisel2-deprecated Issues
documentation link is dead
Closed
3 years ago
Comments count
12
Java Thread Deaths with Tester
Closed
5 years ago
Comments count
2
ccccccglcttvtcigucglvlrgbihthbuurcfiiicudnlj
Closed
5 years ago
Comments count
2
Attaching Analog(X.W) to several Analog(1.W)
Closed
6 years ago
Comments count
1
Is it legal to connect empty bundles?
Closed
7 years ago
Comments count
1
verilator fails to compile small Example
Updated
7 years ago
unable to create a ROM with datawidth more than 64
Closed
7 years ago
Comments count
1
Segmentation fault crashing tester
Updated
8 years ago
Comments count
3
Exception: sbt.TrapExitSecurityException
Updated
8 years ago
Comments count
2
libraryDependencies latest.release not found
Closed
8 years ago
Comments count
2
Queue is not getting synthesized
Updated
8 years ago
RegUpdate and RegReset?
Updated
8 years ago
Comments count
3
abstract type T in type pattern Chisel.Ex[T] is unchecked since it is eliminated by erasure
Updated
8 years ago
Bulk connects do not override bundle components
Updated
8 years ago
Comments count
4
Support bulk connects in `when`?
Updated
8 years ago
Uninferrable width on reg after using fromBits
Updated
8 years ago
Q: "make getting-started" fails
Closed
8 years ago
Comments count
3
firrtl_interpreter/Concrete.scala: randomSInt produces out of bounds value.
Updated
8 years ago
Comments count
2
Vec.fill appears to be badly broken
Closed
8 years ago
Comments count
10
Fill(Chisel.UInt, Int) is in Chisel2, but not supported by Chisel3
Closed
8 years ago
Comments count
1
Will OrderedDecoupledHWIOTester insert bubble for the output.ready signal?
Updated
8 years ago
Comments count
2
OrderedDecoupledHWIOTester doesn't report error when compare failed
Updated
8 years ago
val differs from expression after assignment
Updated
8 years ago
Verilog doesn't use`else` so memory not inferred as RAM
Updated
8 years ago
Comments count
2
Cautionary Tale -- Chisel/ISE issue
Updated
8 years ago
Comments count
3
Inconsistent member names in C++ emulator
Updated
8 years ago
Java Exception (and useless error message) on a Reg of Vec of size 0
Updated
8 years ago
Flag to enable warnings for any modules with any unconnected ports
Updated
8 years ago
Comments count
1
Chisel.TestApplicationException: test application exit - exit code 139
Updated
8 years ago
Comments count
4
Use of "config" as a Chisel value name results in syntax error in Verilog output
Updated
8 years ago
Compilation Error when assigning from other clock
Updated
8 years ago
Comments count
4
Catting a UInt of width 0 leads to strange sim results
Updated
8 years ago
Comments count
1
(Relevant to Enum:) Uppercase identifiers assumed to be stable identifiers in extractor/unapply context
Updated
8 years ago
Testers Vec size issue: java.lang.IndexOutOfBoundsException
Updated
8 years ago
Comments count
2
The <> operator and overriding
Closed
8 years ago
Comments count
1
Warning message needed?
Updated
8 years ago
Make Printf Cycle Accurate
Closed
8 years ago
Comments count
2
C simulation left running if exception in tester
Closed
8 years ago
Comments count
1
Invalid Reg width generation leads to bad bounds in generated Verilog
Updated
8 years ago
Comments count
8
Register size inference
Updated
8 years ago
Comments count
12
Verilog Address Widths Incorrect
Closed
8 years ago
Comments count
8
A question on design
Closed
8 years ago
Comments count
8
Cocotb directives in Verilog backend
Updated
8 years ago
Comments count
2
Width should grow when adding
Closed
8 years ago
Comments count
13
setModuleName is scary... (results in wrong Verilog)
Updated
8 years ago
Comments count
1
Clock dividers / multiclock support
Updated
8 years ago
Comments count
5
tutorial hello asserts sim_api.h:37: channel_t::channel_t(int): Assertion `channel != ((void *) -1)' failed.
Closed
8 years ago
Comments count
4
Negative literal problem
Closed
8 years ago
Comments count
5
More Mem questions
Updated
9 years ago
Comments count
2
Mem Semantics
Updated
9 years ago
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