Giters
ovh
/
sv2chisel
(System)Verilog to Chisel translator
Geek Repo:
Geek Repo
Github PK Tool:
Github PK Tool
Stargazers:
97
Watchers:
18
Issues:
8
Forks:
10
ovh/sv2chisel Issues
Verilog wire should not be converted to chisel Mem()
Closed
2 years ago
Comments count
1
Error: Could not find or load main class sv2chisel.Main
Closed
2 years ago
Comments count
2
A not-found error
Closed
2 years ago
Comments count
5
can not recognize constant
Updated
2 years ago
Comments count
2
parsing issue
Closed
2 years ago
Comments count
3
Function emission does not play nicely with comments
Updated
2 years ago
sv2chisel is adding some unnecessary casts `asTypeOf()`
Updated
2 years ago
sv2chisel is too conservative on parenthesis
Updated
2 years ago