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enjoy-digital
/
litex
Build your hardware, easily!
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2803
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Issues:
788
Forks:
541
enjoy-digital/litex Issues
Issues with main memory > 1GB
Updated
2 months ago
Comments count
1
RISC-V debug module support for CV32E40P/41P ?
Updated
25 days ago
Comments count
3
Trying to interact with UART via Rust binary (stuck at liftoff)
Updated
10 days ago
Comments count
5
Weird builder args behaviour
Updated
3 months ago
Loading binary hangs up
Updated
3 months ago
Comments count
3
default FIFO depth for video is too large for some devices
Closed
a month ago
Comments count
1
Native windows Vivado and WSL2 Litex build fails to find toolchain
Updated
a month ago
Comments count
2
How to set multi-level sequential trigger in litescope ?
Closed
a month ago
Comments count
2
liteeth linux driver performances
Updated
a month ago
Comments count
6
Can't boot linux with MAIN_RAM sizes above 512mb
Updated
a month ago
Comments count
71
UART output not displayed
Updated
3 months ago
Comments count
2
Liteeth: Broken constraints
Closed
a month ago
Comments count
5
litex_sim of CV32E41P is stuck
Updated
a month ago
Comments count
2
Add example for embedding a LiteX SOC into Vivado project for Zynq
Updated
3 months ago
Comments count
4
Restrict bus crossbar access by region mode
Updated
a month ago
Comments count
1
Generated DTS lacks root compatible and model properties
Closed
2 months ago
Comments count
3
Support of MIPS cores
Updated
a month ago
Comments count
1
Support of IO-Link
Updated
a month ago
Support of Interlaken protocol
Updated
a month ago
Support of RapidIO
Updated
a month ago
new Spartan6 programmer
Updated
a month ago
Comments count
2
Xilinx Zynq-7000 digilent_zedboard: workflow failed with meson ERROR: No statements in code.
Updated
5 months ago
Allow CSR paging 0x400
Closed
5 months ago
Comments count
2
NuttX + LiteEth: Potential regression when using Hybrid Etherbone/Ethernet.
Closed
5 months ago
Comments count
8
Windows based build cannot find toolchain support
Closed
6 months ago
Comments count
3
Unexpected behaviour of printf
Updated
6 months ago
Comments count
9
vexriscv_smp: only 32 CSR locations supported with current mem_mam
Closed
4 months ago
Comments count
4
Clock domain crossing for peripherals
Updated
6 months ago
Comments count
3
[Feature request] Support of pmem / Non Volatile Memory
Updated
6 months ago
Comments count
1
tang Nano 9k no uart out
Updated
5 months ago
Comments count
2
LiteScope: more help needed
Updated
6 months ago
Comments count
5
[Feature request] Support to run WebAssembly on FPGA
Updated
6 months ago
Comments count
1
No serial output on tang 9k when selecting other sys-clk-freq
Updated
6 months ago
Comments count
11
Help with LiteScope and jtagbone
Closed
7 months ago
Comments count
5
Wishbone bus high latency in read on Vexriscv CPU "minimal" variant and read/write on others CPU.
Updated
6 months ago
Comments count
3
Make Error *** No rule to make target 'boot-helper.o', needed by 'bios.elf'. Stop. Neorv32 core TUL PYNQ Z2
Closed
7 months ago
Comments count
1
Html doc not generating for TUL PYNQ Z2
Closed
7 months ago
Comments count
2
Missing VCCIO settings for ECP5 when using diamond toolchain
Updated
6 months ago
WSL2 Debian Gowin Toolchain Path
Updated
a month ago
Comments count
5
Failed to modify “boot.c” and the riscv64-unknown-elf/bin/ld report an error “undefined reference to `__heap_start'”
Closed
6 months ago
Comments count
4
Upgrade of the CV32E40P to the openhwgroup repo ?
Updated
a month ago
Comments count
10
The non-ASCII character "…" in README.md may cause failure in setup
Closed
7 months ago
Comments count
1
brew cask install tuntap
Updated
6 months ago
Tang Primer 20k dram issues
Updated
5 months ago
Comments count
23
Python minimum requirement should be updated.
Closed
7 months ago
Comments count
1
netboot
Closed
6 months ago
Comments count
2
Add 64-bit addressing support.
Closed
7 months ago
Comments count
3
What generates `ctrl_bus_errors_read`?
Closed
7 months ago
Comments count
1
Litex sometimes generates unsimulatable verilog
Closed
7 months ago
Comments count
2
How to use Verilator's "forcable" signals
Updated
6 months ago
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