How to use Verilator's "forcable" signals

[hardiselg]

Hello,

I'm trying to use Verilators "forceable" feature, where you could assign signal values through C++ code.

I know how to create the Vforce signals (just add /verilator forceable/ metacomment before ";" to a signal decalration).

The issue is I do not know in which c++ file I could make the assignments.
I tried adding the assignment to Litex/build/sim/gateware/sim_init.cpp generation script, but it gives me this error:
error: invalid use of incomplete type ‘class Vsim___024root’

The assignement itself:
...
sim->rootp->sim__DOT__riscv_core__DOT__alu_operand_a_ex__VforceEn = 0x0000ffff;
*out=sim;

I guess at that stage of compilation the class Vsim___024root is not ready yet.
Does anyone know where is the "correct" place??

*Edit

my "experiments" are done based on this Verialtor test:
t_forceable_var.cpp