No serial output on tang 9k when selecting other sys-clk-freq

Question

No serial output on tang 9k when selecting other sys-clk-freq

rhgndf opened this issue 6 months ago · comments

Running python -m litex_boards.targets.sipeed_tang_nano_9k --build --flash works as expected with the litex bios output seen, but running:

python -m litex_boards.targets.sipeed_tang_nano_9k --build --flash --sys-clk-freq 30e6
python -m litex_boards.targets.sipeed_tang_nano_9k --build --flash --sys-clk-freq 50e6
python -m litex_boards.targets.sipeed_tang_nano_9k --build --flash --sys-clk-freq 54e6

All do not produce any output from the litex bios. The report generated do not seem to have any timing or utilitization issues.

luxuan12512 · Answer 1 · Fri Jan 05 2024 19:47:25 GMT+0800 (China Standard Time)

hello， you can annotation or del the code
kwargs["integrated_rom_size"] = 0
and

self.bus.add_region("rom", SoCRegion(
origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
size = 64*kB,
linker = True)
)
self.cpu.set_reset_address(self.bus.regions["rom"].origin)

rhgndf · Answer 2 · Fri Jan 05 2024 21:15:04 GMT+0800 (China Standard Time)

Hi, I have tried the above and it still doesn't work. Although, finding a solution that doesn't require removing the spiflash XIP code would be nice to free up some BRAMs for other uses.

AndrewD · Answer 3 · Sat Jan 06 2024 06:18:09 GMT+0800 (China Standard Time)

The default --sys-clk-freq is 27mhz which matches the input clock, so if changing --sys-clk-freq doesn't work then then may be an issue with the PLL setup in litex. Are there any warnings from the toolchain?

If you have an oscilloscope you check if the design is working at all by looking for serial output and checking the baud rate.

FYI disabling XIP as per the comment by @luxuan12512 is unlikely to help.

rhgndf · Answer 4 · Sat Jan 06 2024 11:37:01 GMT+0800 (China Standard Time)

One thing to note is that the LED chaser works as expected. However, the UART pins seem to be internally routed in the pcb from the FPGA to the usb programmer chip. Changing baud rates randomly also does not seem to even get garbage outputted. I guess I could try to change the fpga pin assignment to something that is broken out.

There are a lot of warnings but those does not seem related:

Analyzing Verilog file '/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v'
Analyzing Verilog file '/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v'
Compiling module 'sipeed_tang_nano_9k'("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":21)
WARN  (EX3780) : Using initial value of 'builder_interface0_err' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":288)
WARN  (EX3780) : Using initial value of 'main_basesoc_basesoc_adr_burst' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":364)
WARN  (EX3780) : Using initial value of 'main_basesoc_basesoc_ram_bus_err' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":373)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespimmap' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":420)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespimmap_bus_err' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":434)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespimmap_dummy' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":441)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespimmap_source_first' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":448)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespisdrphycore0' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":459)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespisdrphycore1' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":460)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespisdrphycore2' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":461)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespisdrphycore3' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":462)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespisdrphycore_en_int' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":474)
WARN  (EX3780) : Using initial value of 'main_basesoc_litespisdrphycore_source_first' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":490)
WARN  (EX3780) : Using initial value of 'main_basesoc_ram_adr_burst' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":509)
WARN  (EX3780) : Using initial value of 'main_basesoc_ram_bus_ram_bus_err' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":517)
WARN  (EX3780) : Using initial value of 'main_basesoc_rx_source_first' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":538)
WARN  (EX3780) : Using initial value of 'main_basesoc_rx_source_last' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":539)
WARN  (EX3780) : Using initial value of 'main_basesoc_uart_rx_fifo_replace' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":633)
WARN  (EX3780) : Using initial value of 'main_basesoc_uart_tx_fifo_replace' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":691)
WARN  (EX3780) : Using initial value of 'main_basesoc_uart_tx_fifo_sink_first' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":692)
WARN  (EX3780) : Using initial value of 'main_basesoc_uart_tx_fifo_sink_last' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":693)
WARN  (EX3780) : Using initial value of 'main_basesoc_vexriscv' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":745)
WARN  (EX3780) : Using initial value of 'main_hyperram_bus_err' since it is never assigned("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":761)
Extracting RAM for identifier 'rom'("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2454)
Extracting RAM for identifier 'sram'("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2469)
Extracting RAM for identifier 'mem'("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2492)
Extracting RAM for identifier 'storage'("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2508)
Extracting RAM for identifier 'storage_1'("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2529)
WARN  (EX3791) : Expression size 8 truncated to fit in target size 1("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":926)
WARN  (EX3791) : Expression size 8 truncated to fit in target size 1("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1113)
WARN  (EX3791) : Expression size 2 truncated to fit in target size 1("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1121)
WARN  (EX3791) : Expression size 4 truncated to fit in target size 1("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1124)
WARN  (EX3791) : Expression size 8 truncated to fit in target size 1("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1127)
WARN  (EX3791) : Expression size 8 truncated to fit in target size 6("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1381)
WARN  (EX3791) : Expression size 48 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1440)
WARN  (EX3791) : Expression size 30 truncated to fit in target size 2("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1454)
WARN  (EX3791) : Expression size 2 truncated to fit in target size 1("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1457)
WARN  (EX3791) : Expression size 30 truncated to fit in target size 14("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":1486)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2045)
WARN  (EX3791) : Expression size 34 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2048)
WARN  (EX3791) : Expression size 36 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2051)
WARN  (EX3791) : Expression size 40 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2054)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2061)
WARN  (EX3791) : Expression size 34 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2064)
WARN  (EX3791) : Expression size 34 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2067)
WARN  (EX3791) : Expression size 34 truncated to fit in target size 32("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2070)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":2182)
Compiling module 'VexRiscv'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":7)
Extracting RAM for identifier 'RegFilePlugin_regFile'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":1323)
Compiling module 'InstructionCache'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":6021)
Extracting RAM for identifier 'banks_0'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":6127)
Extracting RAM for identifier 'ways_0_tags'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":6128)
Compiling module 'DataCache'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5167)
Extracting RAM for identifier 'ways_0_tags'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5381)
Extracting RAM for identifier 'ways_0_data_symbol0'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5382)
Extracting RAM for identifier 'ways_0_data_symbol1'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5383)
Extracting RAM for identifier 'ways_0_data_symbol2'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5384)
Extracting RAM for identifier 'ways_0_data_symbol3'("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5385)
WARN  (EX3858) : System task 'display' is ignored for synthesis("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5993)
WARN  (EX1998) : Net 'IBusCachedPlugin_cache_io_cpu_fetch_isRemoved' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":67)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_SW' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":81)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_SR' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":82)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_SO' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":83)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_SI' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":84)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_PW' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":85)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_PR' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":86)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_PO' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":87)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_PI' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":88)
WARN  (EX1998) : Net 'dataCache_1_io_cpu_writeBack_fence_FM[3]' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":89)
WARN  (EX1998) : Net 'IBusCachedPlugin_mmuBus_rsp_bypassTranslation' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":604)
WARN  (EX1998) : Net 'dBus_rsp_payload_last' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":617)
WARN  (EX1998) : Net 'DBusCachedPlugin_mmuBus_rsp_bypassTranslation' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":632)
WARN  (EX1998) : Net 'CsrPlugin_mtvec_mode[1]' does not have a driver("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":930)
WARN  (EX1998) : Net 'main_basesoc_litespisdrphycore_dq_i[0]' does not have a driver("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":470)
NOTE  (EX0101) : Current top module is "sipeed_tang_nano_9k"
WARN  (EX0211) : The output port "io_cpu_writeBack_exclusiveOk" of module "DataCache" has no driver, assigning undriven bits to Z, simulation mismatch possible("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5210)
WARN  (EX0211) : The output port "io_cpu_writesPending" of module "DataCache" has no driver, assigning undriven bits to Z, simulation mismatch possible("/.../tang9k/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v":5216)
[5%] Running netlist conversion ...
WARN  (CV0021) : Inout IO_psram_dq[15:8] is unused("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":22)
WARN  (CV0019) : Inout IO_psram_rwds[1] is unused("/.../tang9k/src/build/sipeed_tang_nano_9k/gateware/sipeed_tang_nano_9k.v":23)

rhgndf · Answer 5 · Thu Jan 11 2024 15:10:33 GMT+0800 (China Standard Time)

Did a few more tests, decreasing the frequency works, with output on the uart, but increasing frequency does not.

Gwenhael Goavec-Merou · Answer 6 · Thu Jan 11 2024 15:48:43 GMT+0800 (China Standard Time)

Hi,
When you try to increase clock frequency and you observe this type of behavior it's required to check reports/output from toolchain.
More precisely max frequency is shown in build/sipeed_tang_nano_9k/gateware/impl/pnr/project.tr.html.
And for this board max frequency is around 35/40MHz.
50MHz fails, 35MHz works for me

rhgndf · Answer 7 · Thu Jan 11 2024 18:17:06 GMT+0800 (China Standard Time)

I think I was checking the synthesis results instead of the pnr results. It works now when the pnr passes.

Example synthesis report:

rhgndf · Answer 8 · Thu Jan 11 2024 18:22:42 GMT+0800 (China Standard Time)

Hmm, not quite. At 42MHz the pnr timing passes but there is no output.

PNR report:

Sometimes there is only a single line being output while the cursor moves backwards:
__ _ __ _ __

rhgndf · Answer 9 · Thu Jan 11 2024 22:30:43 GMT+0800 (China Standard Time)

I think this may be a toolchain problem? I'm not sure. There is uart output for the standard cpu configuration at 42MHz but once passing --cpu-variant full the problem above appears. Both of them pass timing verification in the pnr stage, so it's probably not a problem with litex?

Trying --build --flash a few times gets a working bitstream. Timing failed once, but the other runs which didnt work all have 0 negative slack, so it might be that the toolchain isn't working well when the frequency is too high.

enjoy-digital · Answer 10 · Fri Jan 12 2024 16:41:28 GMT+0800 (China Standard Time)

@rhgndf: It would be interesting to output a divided version of the clock to one of the pin of the board and observe it with a scope and do the same for the UART TX. If correct, this would exclude PLL configuration issues and if not, we would need to check the PLL.

rhgndf · Answer 11 · Fri Jan 12 2024 18:55:44 GMT+0800 (China Standard Time)

The board has an LED chaser, which is probably close enough? The LEDs light up at approximately the correct timing as far as I can tell.

It seems like it might be data corruption somewhere since in the failed attempts, it outputs BIOS CRC Error.