vexriscv_smp: only 32 CSR locations supported with current mem_mam
AndrewD opened this issue · comments
The current memory map allows for 32 CSR locations:
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
This can be expanded to 64 by specifying --csr-address-width=15
, however the cpu mem_map places clint straight after csr
"csr": 0xf000_0000,
"clint": 0xf001_0000,
So this causes the following build error:
ERROR:SoCBusHandler:Region overlap between clint and csr:
ERROR:SoCBusHandler:Origin: 0xf0010000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
ERROR:SoCBusHandler:Origin: 0xf0000000, Size: 0x00020000, Mode: RW, Cached: False Linker: False
Can the mem_map be adjusted easily to support additional CSR locations?
Hi,
True: CSR region is a bit small.
With #1876 it is possible to move CSR/CLINT/PLIC (and consequently it's possible to increase CSR region).
This may be done by overriding region directly from the target and/or by passing region base address using CLI args.
Is this solution is good to you?
Thanks @AndrewD for the feedback.