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enjoy-digital
/
litex
Build your hardware, easily!
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2756
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97
Issues:
781
Forks:
534
enjoy-digital/litex Issues
#1833 breaks Tang nano 9k, as it generates illegal code
Updated
5 months ago
Comments count
1
opensbi
Closed
5 months ago
Comments count
3
Thoughts on skipping interrups problem, on gowin / vexrisc platform
Closed
7 months ago
Comments count
4
json2dts issue
Updated
4 months ago
Comments count
5
How to generate DMA in litex
Updated
5 months ago
Comments count
1
PR #1817 may have broken AXI-lite peripheral interconnect
Closed
6 months ago
Comments count
13
Broken QMtech Altera boards
Closed
7 months ago
Comments count
2
litex_term image load stucked on Genesys2
Updated
5 months ago
Physical constraint problem on tang_primer_20k
Updated
5 months ago
Comments count
3
clocker_storage_reg -> ODDR timing issue
Closed
a month ago
Comments count
20
sys_rst timings on large SoC
Closed
7 months ago
Comments count
6
I got the error: ‘class VerilatedVcdC’ has no member named ‘set_time_unit’. How to fix it?
Updated
5 months ago
Comments count
1
RFC: register new Interrupt Service Routine (ISR) funtions for additional interrupts
Closed
7 months ago
Comments count
2
How to drive `soc_rst` from an external pin?
Closed
8 months ago
Comments count
4
How to add a driver controller interrupt in Zephyr RTOS for LiteX SoC with 64-bit CVA6 cpu ?
Closed
8 months ago
Comments count
1
NEORV32 Memory initialization failed on Arty A7-100T
Updated
5 months ago
Comments count
2
OSError: Unable to find valid Meson build system, please install it with: - pip3 install meson.
Closed
8 months ago
Comments count
2
IOStandard missing for Efinix PLL clock reference
Updated
5 months ago
Comments count
2
coremark test of VexRiscv SMP on Sipeed Tang Primer 20K
Closed
8 months ago
Comments count
1
litex_bare_metal_demo on litex_sim (cva6) hanging after liftoff
Updated
5 months ago
Comments count
1
Issues in Tang_mega_138k
Closed
8 months ago
Comments count
1
Zephyr: DTS generation fail on vexriscv (target: xilinx_zcu102)
Closed
5 months ago
Comments count
2
Xilinx zcu102 build failure
Closed
9 months ago
Comments count
1
litex_json2renode.py --bios-binary doesn't load bios to rom - wiki example doesn't work
Closed
9 months ago
Feature request: ADAT I/O
Updated
5 months ago
.
Closed
8 months ago
Combinatorial signal with single slice assignment loses default ("reset") value
Closed
9 months ago
Pynq Z1 Terminal
Closed
9 months ago
Comments count
4
issue when boot on tang-primer-20k
Closed
9 months ago
NameError: name 'Signal' is not defined
Closed
9 months ago
Comments count
9
ERROR: Project file:///home/riscv/python-litex/migen has a 'pyproject.toml' and its build backend is missing the 'build_editable' hook. Since it does not have a 'setup.py' nor a 'setup.cfg', it cannot be installed in editable mode. Consider using a build backend that supports PEP 660.
Closed
5 months ago
Comments count
4
AXI4 -> Litedram write mask issue
Closed
9 months ago
Comments count
3
Simulink-like design environment
Updated
5 months ago
Comments count
4
Understanding the evolution of LiteX and deduplicating code
Closed
9 months ago
Comments count
3
vexriscv with hyperram, fpu and coherent dma with broken by commit f473261bc6b
Closed
10 months ago
Comments count
1
litex/gen/sim: add generate_gtkw_savefile() as per simsoc to VCDWriter or Simulator
Updated
5 months ago
Zephyr support on LiteX/NaxRiscv
Closed
9 months ago
Comments count
2
RocketChip: MEM port to LiteDRAM width matching (internal vs. LiteX AXIUpConverter)
Updated
6 months ago
Comments count
14
Various Issues with Sipeed Tang Primer 20k
Updated
5 months ago
Comments count
38
RocketChip with L2 cache - works in litex sim, works on digilent nexys video with cpu-mem-width is 64, breaks with 128
Updated
6 months ago
Comments count
10
Wishbone L2 cache specs
Closed
9 months ago
Comments count
4
Code for stub UART instantiation looks wrong
Closed
a year ago
Comments count
1
booting hangs when using integrated sram to load code
Closed
a year ago
Comments count
6
Non existent interrupts can be added using self.irq.add()
Updated
a year ago
PoC for using Amaranth's FHDL compat mode as alternative to Migen's FHDL.
Updated
a year ago
Comments count
4
--sys-clk-freq=48e6 does not work on Arty
Closed
a year ago
Comments count
4
ttyUSBX missing when trying to use litex_term to load code
Closed
a year ago
Comments count
4
Problem when adding my VHDL module to litex
Closed
a year ago
Comments count
2
.repl and .resc files for Renode cannot be created from Litex
Closed
5 months ago
Comments count
2
no uart when changing sys-clock-freq
Closed
a year ago
Comments count
2
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