Litex sometimes generates unsimulatable verilog

[Rowan Goemans]

The verilog was generated from https://github.com/rowanG077/liteeth-16-byte-bug/tree/testing

with the commands:

./colorlite.py --ip-address=10.0.11.43 --build
./sim.sh

Ignore the nextpnr error. The important part is the verilog is generated. This shows a simulation that makes no progress.

See steveicarus/iverilog#1028 for the details and a cut down verilog example.

[enjoy-digital]

Can you try with regular_comb=False: https://github.com/enjoy-digital/litex/blob/master/litex/gen/fhdl/verilog.py#L566?

[Rowan Goemans]

Can confirm that with that option it works.