diningyo

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-book

Digital Design with Chisel

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

svls

SystemVerilog language server

sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

svlint

SystemVerilog linter

berkeley-hardfloat

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

berkeley-softfloat-3

SoftFloat release 3

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

advanced-computer-organization

tnoc

Network on Chip Implementation written in SytemVerilog

kami

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

riscv-rust-toolchain

RISCV Rust Toolchain

sv2chisel

(System)Verilog to Chisel translator

riscv-newlib

RISC-V port of newlib

sha3

firechip

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

firrtl-interpreter

A scala based simulator for circuits described by a LoFirrtl file

zoom

🔍 Zoomable Waveform viewer for the Web

chisel-cheatsheet

Chisel Cheatsheet

svls-vscode

SystemVerilog language server client for Visual Studio Code

risc-v

RISC-VのCPU作った

chisel-coverage

A coverage library for Chisel designs

tinysixel

A tiny header-only C++ library for Sixel.

yosys

Yosys Open SYnthesis Suite

biblio_doc

vcd2step

Converts a VCD file to a Chisel tester input file