riscv / riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

https://jira.riscv.org/browse/RVG-94

riscv/riscv-debug-spec Issues

How to reset the DM on the first connection on both 0.13 and 1.0 spec versions
Updated 19 days ago6
Ambiguous requirement about dmcontrol behavior when dmcontrol.dmactive==0
Closed 22 days ago2
Why debugger lose control of the hart while executing a program not terminate with an ebreak instruction
Closed 25 days ago
Trigger match on csrrs/csrrc to tdata1
Updated a month ago13
Cross Trigger definition in RISC-V
Updated a month ago3
How to halt or resume multiple harts simultaneously?
Updated a month ago4
Hit bit interaction with action conflict when several triggers of the same priority match
Updated a month ago3
A typo in [5.4. Native Triggers]
Closed a month ago1
Stored value availability to TM in case of AMOs
Updated a month ago6
`mcontrol' / 'mcontrol6` `match=lt` trigger on the last valid address
Closed a month ago6
Timing requirements for a chain of `mcontrol` load address triggers
Updated a month ago2
`maskmax6` discovery may need clarification
Updated a month ago2
Table cell justification/alignment issues
Closed a month ago1
NAPOT matching
Closed a month ago2
Typo on the minimum requirements of Debug Mode
Closed a month ago4
Does *stateen0[57] control mscontext if implemented?
Closed 2 months ago2
Typo/mistake in "Debug Mode" section/mprven
Closed 2 months ago1
Clarification of register needed
Closed 2 months ago1
Q about Table 9 (action encoding)
Updated 2 months ago8
Register bit-field bit offset numbers clipped
Updated 2 months ago2
Clarify effect of tdata1 write with zero when only one trigger type supported
Updated 2 months ago5
Duplicate register field layout diagram for `tdata1`
Closed 2 months ago1
Priority of mcontrol/mcontrol6 load data before trigger
Updated 3 months ago1
Discovery of incompatible base ISAs
Updated 3 months ago13
How to define the action of hcontext or textra32's action, when H extemsion is enabled or disabled by setting misa[7].
Closed 3 months ago2
Does mcontrol6.hit affect future trigger firing
Closed 3 months ago1
tmexttrigger clarification
Closed 3 months ago1
misleading sbdata0 description
Updated 3 months ago1
Minor asciidoc conversion problem
Closed 3 months ago
Priority of various cmderrs
Updated 3 months ago
"$" characters in asciidoc
Closed 4 months ago3
asciidoc lacks lists of figures and tables
Updated 4 months ago1
clarifications on sdext and sdtrig extensions
Updated 4 months ago1
how to modify code in debug mode in riscv
Updated 4 months ago2
Sdtrig: state of triggers when debugged process moves to another CPU
Closed 4 months ago5
abstract register command and aarsize restrictions
Updated 5 months ago21
Contradictory requirements for dmcontrol.ndmreset=1
Updated 5 months ago5
Clarify JTAG IDCODE requirement in an SOC
Closed 5 months ago7
Clarify the feature of reset
Closed 6 months ago5
Behaviour of triggers after hart reset
Updated 6 months ago30
what does haltsum0: LSB/MSB mean?
Closed 6 months ago2
Clarification on updating the uncertain bit
Closed 6 months ago1
Is mcontrol6 trigger allowed to fire on prestart, inactive, and tail elements of vector load/store?
Closed 6 months ago2
For interrupt and exception triggers with action = 0, what value for mcause?
Closed 8 months ago14
For MXLEN=32, can't trigger on interrupts 32 or higher
Closed 8 months ago2
For MXLEN=32, can't trigger on exceptions 32 or higher
Updated 8 months ago5
Exception priority table should be consistent with latest Priv Spec
Closed 8 months ago
What purpose does the external trigger input named intctl serve?
Closed 8 months ago2
Why does an instruction count trigger also count traps?
Closed 8 months ago3
Does "this section" mean "this chapter"?
Closed 8 months ago1