diningyo

dirv

This is my first trial project for designing RISC-V in Chisel

introductory-guide-to-chisel

「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ

crypto

Crypto modules in Chisel.

learning-chisel3

Repository for learning Chisel3

chisel-ci

ChiselのCI環境を構築するためのお試し環境

fpga-scr1

fpga simulation and synthesis for scr1 which designed by syntacore

chisel-actions

Chisel actions

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chisel-bootcamp-exercise

vivado simulation environment for chisel-bootcamp exercise code written by verilog

chisel-dmg

dsim_trial

Trial environment for DSim

chisel-template

A template project for beginning new Chisel work

chisel-testers

Provides various testers for chisel users

chisel3

Chisel 3: A Modern Hardware Design Language

chisel3-wiki

Mirror of Chisel3 Github wiki https://github.com/ucb-bar/chisel3/wiki

elixir-dmg

Gameboy emulator in Elixir

fpga-ram-gen

InferenceRAM generator for Xilinx FPGA

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

hello-world-docker-action

https://help.github.com/ja/articles/creating-a-docker-container-action を試す

hw-impl-base

misc-data

programming-elixir

プログラミングElixirの勉強用

rocket-chip

Rocket Chip Generator

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

scr1-sdk

open-source SDK for SCR1 core

trial-tjctm24028-spi

Trial for TJCTM24028-SPI

ultra96_trial

Avnet Ultra96 trial

www.chisel-lang.org

The home of the Chisel3 website