set-associative-cache

There are 1 repository under set-associative-cache topic.

• tugrul512bit / LruClockCache

  A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.

  lrulru-cachelow-latencycachingclock-second-chancecppleast-recently-usedmemoizationdata-structuresbenchmarkmulti-level-cachedirect-mapped-cachecache-simulatorcachefastfastesthigh-performancehigh-throughputlow-latency-queriesset-associative-cache
  Language:C++ 71

• avikram2 / RISCVPipelinedProcessor

  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.

  cachepipelined-processorspipelined-riscriscv32set-associative-cachevictim-cache
  Language:Verilog 9

• yadav-sachin / Multilevel-Cache-Controller

  Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy. Implemented on a Basys3 Artix-7 FPGA with proper delays and hit signals.

  cache-controlset-associative-cachewrite-backlru-cachebasys3-fpgafour-way-set-associative
  Language:Verilog 8

• Swap76 / Cache_Mapping_Technique

  Simulator for Direct, Associative, Set Associative Mapping Technique in Cache Allocation

  c-plus-pluscache-simulatordirect-cacheassociative-cacheset-associative-cachecache-mapping
  Language:C++ 5

• anoushkanarang / Cache-Mapping

  Storing data in 16-bit multilevel Direct Mapped, Associative, N-way Set Associative cache memory

  cache-simulatorcachecomputerorganizationassociative-cachedirect-cacheset-associative-cache
  Language:Java 3

• niksram / Cache-Mapping-Simulator

  The following program here helps in simulating how blocks from main memory can get mapped to cache based on strategies: Direct-Mapping, Fully-Associative, Set-Associative

  cache-simulatorcache-storageset-associative-cachedirect-cache
  Language:C++ 3

• paulmooreparks / SetAssociativeCache

  C# implementation of a set-associative cache with multiple policies (LRU, LFU, etc.)

  set-associativecacheset-associative-cachecsharpcsharp-librarydotnetdotnet-core
  Language:C# 3

• 0mega28 / TLB-Controller

  2-level TLB Controller

  2-level-cacheexclusive-designleast-recently-used-cacheset-associative-cachetlb-simulator
  Language:C++ 1

• himanshu5-prog / cache_implementation

  The repository simulates direct-mapped and four way set associative cahe.

  cachecache-simulatorcomputer-architecturedirect-mapped-cacheset-associative-cache
  Language:C++ 1

• franciscofpereira / DualCacheSimulator

  Dual hierarchy (L1 and L2) cache simulator with direct mapping and two way associative configurations. Project for Computer Organization class.

  direct-mapped-cacheset-associative-cachecache-simulator
  Language:C 0

• poofypigeon / cache-controller

  Fully parametric Set Associated Cache with a Pseudo Least Recently Used replacement policy implemented in VHDL.

  cacheplruset-associative-cachevhdl
  Language:VHDL 0

• rgongw0414 / Set-Associative-Cache

  Simulation of Set Associative Cache

  set-associative-cacheassociative-cachecachecomputer-architecture
  Language:Python 0

• GSri30 / CacheImplementation

  A simple implementation of a Direct Mapped Cache and Set Associative Cache in C++. Supports for different sizes of the cache, block, #ways, etc.

  cacheset-associative-cachedirect-mapped-cachedynamic-sizetracescppbitset
  Language:C++