Ayush Vikram's repositories
RISCVPipelinedProcessor
Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
Complex-Number-Bot
Code for a Discord Complex Number Bot
CS380AdvancedOS
repo for assignments from the Advanced OS CS 380 L Course from UT Austin MS CS
DesignofAlgorithmsSolutions
Solutions for Exercises in Data Structures and Algorithms by Aho, Hopcroft, and Ullman, 1987
Microsoft-MPI
Microsoft MPI
Moneo
Distributed AI/HPC Monitoring Framework
NaiveBayesReviewClassifer
Project for INFO 490 MH2 class at UIUC
PacmanFPGA
ECE 385 Final Project on DE-10 FPGA Board with NIOS 2 SoC: Implementing PacMan
RedisAndMemcached
Working with Redis and Memcached
rocm_bandwidth_test
Bandwidth test for ROCm
SpecialRelativity
Code dealing with Special Rel topics, such as code to perform the Lorentz Trasformation
WDLCromwell
getting familiar with WDL and Cromwell