Merin Yeldho's repositories
Low-Power-and-Area-Efficient-Carry-Select-Adder-CSLA-
Verilog implementation modified carry select adder
SAP1-computer-verilog
Verilog implementation of SAP-1 computer architecture
Merinyeldho
Config files for my GitHub profile.
000
Multilingo-Translator
Translator
Language:JavaScript000
Language:HTML000
Language:C++000