There are 1 repository under fpga-verilog topic.
Projects implemented in Spartan3 and Spartan3e for the Digital Systems class
This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.