Hicret Erkoç's repositories
awesome
A curated list of awesome resources for HDL design and verification
awesome-opensource-hardware
List of awesome open source hardware tools, generators, and reusable designs
esnet-fpga-library
ESnet general-purpose FPGA design library.
OpenFASOC
Fully Open Source FASOC generators built on top of open-source EDA tools
verilog-axi
Verilog AXI components for FPGA implementation
spi-to-axi-bridge
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
fpga_screensaver
This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board.
spi-master
SPI Master for FPGA - VHDL and Verilog
AXI4Bus
一套AXI4 interconnect 组件,通过简单连接可以搭建需要的AXI interconnect。
spi_slave_simple
Simple System Verilog implementation of SPI Slave
verilog-uart
Verilog UART
vscode-hyhdl
VScode extention: instantiation, testbench, documentation for verilog
FPGA_MCU_SPI_COM
Simple SPI-based communication between FPGA and MCU, using EP4CE15 and STM32F407 as an example
SPIglass
A fully synthesizable, BRAM backed SPI Flash device
Cores-SweRV
SweRV EH1 core
awesome_photonics
😎 curated list of open source photonics projects
meep
free finite-difference time-domain (FDTD) software for electromagnetic simulations
cmod_a7_spi_sram
SPI slave to External SRAM interface for Cmod A7
adc_block_ram_spi_top
Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.
QuadSPI
RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.
SiPANN
Artifical Neural Networks for use with Quantum Photonics
AXI4_Master_Interconnect_Slave
A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.
Dual-Core-RISC-V-Processor
A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.
MIPS-CPU-fork
A Simulative MIPS CPU running on Logisim.