Simple SystemVerilog implementation of SPI Slave
The MSB on MOSI is the Read/Write bit (WR).
Write = 0, Read = 1
This is followed by an address field of parametrized length, followed by a data field of parameterized length which is on MOSI if RW was 0, or returned from the target on MISO if RW bit was 1.
The packetsize, header, and payload size are parameteters which can be changed. Defaults:
parameter int pktsz = 16, // size of SPI packet
parameter int header = 8, // size of header
parameter int payload = 8, // size of payload
parameter int addrsz = 7 // size of SPI Address Space
Name | Type | Width | Description |
clk | Input | 1 | System Clock. SCLK is oversampled. clk must be > 4x SCLK. |
reset_n | Input | 1 | asynchronous reset (active low) |
SCLK | Input | 1 | Serial Clock Input for SPI |
SSB | Input | 1 | SPI Select |
MOSI | Input | 1 | Master Out Slave In |
MISO | Output | 1 | Master In Slave Out |
tx_d | Input | payload | Data to transmit to host on MISO. Parameter. Default is 8 bits |
tx_en | Input | 1 | |
addr | Output | addrsz | register/memory for controller to access. Parameter. Default is 7 bits |
addr_dv | Output | 1 | Signals when address is valid |
rx_d | Output | payload | Data bits received from host during payload part of SPI frame. Parameter, 8 bits default. |
rx_dv | Output | 1 | Signals when rx_d is valid. |
rw_out | Output | 1 | Read/Write Out. Signals whether frame is a read transaction or write transaction. RW == 0 means this block determined 1st bit (RW) was zero; Write data on MOSI from Host (master) to Target (slave) at address . RW== 1 means send data on MISO from target at to host |
Simulation -- testbench checked using ModelSim - INTEL FPGA STARTER EDITION 2020.1 Revision: 2020.02
this design was tested on an Intel MAX 10 FPGA 10M50 Evaluation Kit Board with a Raspberry Pi acting as SPI Host. See validation directory.