RISC-V (riscv)

RISC-V

riscv

Geek Repo

The Free and Open RISC Instruction Set Architecture

Location:Zurich, CH

Home Page:https://riscv.org

Twitter:@risc_v

Github PK Tool:Github PK Tool

RISC-V's repositories

riscv-isa-manual

RISC-V Instruction Set Manual

Language:TeXLicense:CC-BY-4.0Stargazers:3376Issues:203Issues:767

riscv-opcodes

RISC-V Opcodes

Language:PythonLicense:BSD-3-ClauseStargazers:625Issues:86Issues:57

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

Language:PythonLicense:NOASSERTIONStargazers:439Issues:73Issues:410

sail-riscv

Sail RISC-V model

Language:CoqLicense:NOASSERTIONStargazers:404Issues:42Issues:200

riscv-openocd

Fork of OpenOCD that has RISC-V support

Language:CLicense:NOASSERTIONStargazers:397Issues:57Issues:320

meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

Language:BitBakeLicense:NOASSERTIONStargazers:340Issues:37Issues:111

learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

riscv-j-extension

Working Draft of the RISC-V J Extension Specification

Language:MakefileLicense:CC-BY-4.0Stargazers:154Issues:34Issues:58

riscv-profiles

RISC-V Architecture Profiles

Language:MakefileLicense:CC-BY-4.0Stargazers:90Issues:24Issues:128

docs-dev-guide

Documentation developer guide

Language:TeXLicense:CC-BY-4.0Stargazers:78Issues:18Issues:15

riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.

Language:MakefileLicense:CC-BY-4.0Stargazers:78Issues:14Issues:74

riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Language:PythonLicense:CC-BY-4.0Stargazers:27Issues:15Issues:112
Language:MakefileLicense:CC-BY-4.0Stargazers:25Issues:11Issues:26

riscv-smmtt

This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.

Language:MakefileLicense:CC-BY-4.0Stargazers:24Issues:9Issues:24
Language:MakefileLicense:CC-BY-4.0Stargazers:18Issues:6Issues:13

riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

Language:MakefileLicense:CC-BY-4.0Stargazers:13Issues:8Issues:16

riscv-smbios

RISC-V SMBIOS Type 44 Spec

Language:TeXLicense:CC-BY-4.0Stargazers:13Issues:14Issues:3

riscv-zabha

The Zabha extension provides support for byte and halfword atomic memory operations.

Language:MakefileLicense:CC-BY-4.0Stargazers:7Issues:8Issues:9

riscv-docs-base-container-image

A base container image populated with the dependencies to build the RISC-V Documentation.

riscv-zilsd

Zilsd (Load/Store Pair for RV32) Fast-Track Extension

Language:MakefileLicense:CC-BY-4.0Stargazers:6Issues:5Issues:11

riscv-b

"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions

Language:MakefileLicense:CC-BY-4.0Stargazers:4Issues:4Issues:2

riscv-zaamo-zalrsc

Zaamo / Zalrsc: A extension components

Language:MakefileLicense:CC-BY-4.0Stargazers:4Issues:5Issues:4

riscv-performance-events

RISC-V Performance Events Specification

Language:MakefileLicense:CC-BY-4.0Stargazers:2Issues:3Issues:0

riscv-ssqosid

This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.

Language:MakefileLicense:CC-BY-4.0Stargazers:2Issues:4Issues:0

riscv-svvptc

Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)

Language:MakefileLicense:CC-BY-4.0Stargazers:2Issues:4Issues:0

riscv-dot-product

Dot-Product Extension

Language:MakefileLicense:CC-BY-4.0Stargazers:1Issues:4Issues:0

riscv-smcdeleg-ssccfg

Supervisor Counter Delegation Architecture Extension

Language:MakefileLicense:CC-BY-4.0Stargazers:1Issues:5Issues:0

riscv-ssdtso

The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.

Language:MakefileLicense:CC-BY-4.0Stargazers:1Issues:7Issues:0