RISC-V (riscv)

RISC-V

riscv

Geek Repo

The Free and Open RISC Instruction Set Architecture

Location:Zurich, CH

Home Page:https://riscv.org

Twitter:@risc_v

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RISC-V's repositories

riscv-isa-manual

RISC-V Instruction Set Manual

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riscv-opcodes

RISC-V Opcodes

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riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

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sail-riscv

Sail RISC-V model

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meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

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learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

riscv-j-extension

Working Draft of the RISC-V J Extension Specification

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riscv-profiles

RISC-V Architecture Profiles

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riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.

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docs-dev-guide

Documentation developer guide

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configuration-structure

RISC-V Configuration Structure

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riscv-smmtt

This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.

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riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

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riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

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riscv-double-trap

RISC-V Double Trap Fast-Track Extension

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riscv-zabha

The Zabha extension provides support for byte and halfword atomic memory operations.

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riscv-docs-base-container-image

A base container image populated with the dependencies to build the RISC-V Documentation.

riscv-zilsd

Zilsd (Load/Store Pair for RV32) Fast-Track Extension

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riscv-b

"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions

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riscv-zaamo-zalrsc

Zaamo / Zalrsc: A extension components

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riscv-performance-events

RISC-V Performance Events Specification

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riscv-zalasr

The ISA specification for the Zalasr extension.

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composable-extensions

This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.

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riscv-memory-tagging

Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores

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sail-asciidoc

The repository that hosts the integration between SAIL and Asciidoc

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