RISC-V's repositories
riscv-isa-manual
RISC-V Instruction Set Manual
riscv-opcodes
RISC-V Opcodes
riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard
sail-riscv
Sail RISC-V model
meta-riscv
OpenEmbedded/Yocto layer for RISC-V Architecture
riscv-fast-interrupt
Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
riscv-j-extension
Working Draft of the RISC-V J Extension Specification
riscv-profiles
RISC-V Architecture Profiles
riscv-cfi
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.
docs-dev-guide
Documentation developer guide
riscv-cheri
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
configuration-structure
RISC-V Configuration Structure
riscv-smmtt
This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
riscv-control-transfer-records
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
riscv-double-trap
RISC-V Double Trap Fast-Track Extension
riscv-spmp
The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
riscv-docs-base-container-image
A base container image populated with the dependencies to build the RISC-V Documentation.
riscv-zilsd
Zilsd (Load/Store Pair for RV32) Fast-Track Extension
riscv-performance-events
RISC-V Performance Events Specification
riscv-dot-product
Dot-Product Extension
riscv-svvptc
Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)
composable-custom-extensions
This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
ft-trigger-delegation
Trigger Delegation Fast-Track Specification
self-hosted-trace
RISC-V Self-hosted Trace Development Fork