riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

riscv/riscv-fast-interrupt Issues

Missing a catchy terminology for the selection priority
Updated 20 days ago
Add optional support for hardware register save e.g. shadow register sets?
Updated a month ago3
Moving CLIC memory mapped registers to indirect CSRs
Updated 2 months ago16
Require immediate evaluation of clicintie and clicintip
Updated 2 months ago10
Tentative assignment of base value of miselect/siselect for CLIC
Closed 3 months ago2
How should non-normative text be specified in CLIC spec
Updated 3 months ago5
Allow fixed configuration for some fields
Closed 3 months ago5
clicintctl/clicintattr miselect offsets are incorrect
Closed 3 months ago1
Is CLIC register access via indirect CSR Access mandatory?
Closed 3 months ago1
Titles of indirect register access sections
Closed 3 months ago1
xnxti with HW- and SW-vectored interrupts
Closed 3 months ago1
smclicshv and the Next Interrupt Handler Address and Interrupt-Enable CSRs (xnxti)
Closed 3 months ago1
clicintctrl vs. clicintctl
Closed 3 months ago1
do we really want this CLINT mode xnxti behavior?
Closed 3 months ago2
smclicshv - Software vectoring only allowed when hardware vectoring is disabled?
Closed 3 months ago8
clicinttrig behavior when the interrupt is claimed by xnxti
Closed 3 months ago4
Smstateen bit
Closed 4 months ago4
Behavior of interrupt pending bit for disabled interrupts
Closed 4 months ago1
Any higher priority interrupt causes xnxti service loop exit
Closed 6 months ago4
How are CLIC-only CSRs and fields handled in CLINT mode?
Closed 6 months ago3
xcause.inhv conflicts with enabling CLIC per mode
Updated 8 months ago2
NUM_INTERRUPT listed as a parameter in two sections
Closed 8 months ago1
Is there a specification for mnstatus.mpp and mnstatus.mpie?
Closed 8 months ago4
exception_handler pseudocode needs checking
Closed 8 months ago
Clearing of xinhv after a successful xRET
Closed 8 months ago
Wrong indentation?
Closed 8 months ago1
Side effects of executing mret with mcause.minhv==1
Closed 8 months ago7
CLICINTCTLBITS significance
Closed 8 months ago2
value of sintthresh when mret is called
Closed 8 months ago1
Question about xinhv
Closed 10 months ago10
xcause.xpil and xpie behavior on trap taken and xRET
Closed 9 months ago4
stateen register required to block access to new ssclic CSRs?
Closed 9 months ago1
Existence of mscratchcsw on a machine mode only CPU?
Closed 9 months ago1
Reserved ranges in memory mapped registers
Closed 9 months ago1
Automatically clear xintthresh.th
Closed a year ago2
Clean up section 9.1.1. (xcliccfg registers)
Closed a year ago1
Clearing xintthresh when fewer than 8 threshold bits are implemented
Closed a year ago2
clarify interaction of CLIC with RNMI
Closed a year ago2
Clarification on trampoline examples and callee-save expectation for non-x registers
Closed a year ago2
should xintthresh be initialized to 0?
Closed a year ago2
Consistently use ABI names for registers
Closed a year ago1
MNRET and mintthresh
Closed a year ago1
xintthresh checks on entry from lower privilege levels
Closed a year ago7
Clarify changes to CLIC memory-mapped registers
Closed a year ago3
behavior/arrangement of mcliccfg.nlbits/scliccfg.nlbits/ucliccfg.nlbits
Closed a year ago2
Typos in preemptible horizontal interrupt handler
Closed a year ago1
Interrupt level behavior for NMIs
Closed a year ago
Descriptions of xideleg and xedeleg look incorrect
Closed a year ago1
Redundant note in smclicshv section
Closed a year ago1
The year of the cover is wrong
Closed a year ago1