nishit0072e / Enc_Dec_Xor

8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.

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RTL Design: ๐Ÿ‘‡ RTL Simulation Waveform: ๐Ÿ‘‡ Screenshot 2023-10-11 221430

Enc_Dec_Xor

8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.

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8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.


Languages

Language:Verilog 58.8%Language:Tcl 41.2%