Nishit Bayen's starred repositories
AES_in_verilog
An algorithmic state machine verilog code for AES Encryption/Decryption Algorithm
16-bit-processor
Processor code, assembly code to noise filter and downsample an image, Instruction Set Architecture files available
8-bit_fpga_cpu
An 8-Bit CPU implemented in an FPGA
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Inverter-design-and-analysis-using-sky130pdk
Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
VLSI-Fundamentals-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
100DaysOfRtlDesign
I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
eSim-Cloud
A web-based system for designing and simulating electronic (eSim) and Arduino circuits.
RTL-Coding
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"