iammituraj / apb

APB master and slave developed in RTL.

apb

APB master and slave developed in System Verilog.

Source codes included

apb_master : APB master
apb_slave0.sv: APB slave with zero wait states
apb_slave.sv : APB slave with one wait state
tb.sv : Testbench

Comments

All source codes are fully synthesizable and tested. All source codes are open-source, free to use, modify, and distribute without any conflicts of interest with the original developer.

Developer

Mitu Raj, [e-mail]