iammituraj

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Chipmunk Logic™

India

https://chipmunklogic.com

Mitu Raj's repositories

pequeno_riscv

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Language:SystemVerilogNOASSERTION56 4 1

FIFOs

Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

Language:SystemVerilog15 20

pqr5asm

PQR5ASM is a RISC-V Assembler compliant with RV32I

Language:PythonNOASSERTION14 30

skid_buffer

Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

Language:SystemVerilog14 10

apb

APB master and slave developed in RTL.

Language:SystemVerilog10 10

debouncer

Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.

Language:SystemVerilog6 20

LIFO-Stack

Register-based LIFO aka Stack designed in Verilog/System Verilog.

Language:SystemVerilog4 10

reset_and_cdc_synchronizers

Reset and CDC synchronizers developed in Verilog/System Verilog.

Language:SystemVerilog3 1 1

gcd_calculator

GCD calculator with APB Slave interface.

Language:SystemVerilog2 20

iammituraj

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style-guides

lowRISC Style Guides

CC-BY-4.0000

tweak_circuits

Tweak circuits designed in VHDL/Verilog like CDC synchronizers: Pulse synchronizer, Reset synchronizer, Two-flop synchronizer, Edge detectors, Pulse generators, Clock gating etc.

Language:VHDL010