Mitu Raj (iammituraj)

iammituraj

Geek Repo

Company:Chipmunk Logic™

Location:India

Home Page:https://chipmunklogic.com

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Mitu Raj's repositories

pequeno_riscv

Pequeno aka PQR5 is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

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FIFOs

Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

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skid_buffer

Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

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pqr5asm

PQR5ASM is a RISC-V Assembler compliant with RV32I

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debouncer

Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.

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LIFO-Stack

Register-based LIFO aka Stack designed in Verilog/System Verilog.

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reset_and_cdc_synchronizers

Reset and CDC synchronizers developed in Verilog/System Verilog.

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gcd_calculator

GCD calculator with APB Slave interface.

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style-guides

lowRISC Style Guides

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tweak_circuits

Tweak circuits designed in VHDL/Verilog like CDC synchronizers: Pulse synchronizer, Reset synchronizer, Two-flop synchronizer, Edge detectors, Pulse generators, Clock gating etc.

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