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I got the error: ‘class VerilatedVcdC’ has no member named ‘set_time_unit’. How to fix it?

KiemKhiem opened this issue · comments

commented 
make -j -C /home/khiem/Desktop/Litex/build/sim/gateware/obj_dir -f Vsim.mk Vsim
make[1]: Entering directory '/home/khiem/Desktop/Litex/build/sim/gateware/obj_dir'
g++  -I.  -MMD -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable     -ggdb -Wall -O3   -I/home/khiem/Desktop/Litex/litex/litex/build/sim/core   -c -o veril.o /home/khiem/Desktop/Litex/litex/litex/build/sim/core/veril.cpp
g++  -I.  -MMD -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable     -ggdb -Wall -O3   -I/home/khiem/Desktop/Litex/litex/litex/build/sim/core   -c -o sim_init.o ../sim_init.cpp
g++  -I.  -MMD -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable     -ggdb -Wall -O3   -I/home/khiem/Desktop/Litex/litex/litex/build/sim/core   -c -o verilated.o /home/khiem/optimsoc/prebuilt/verilator-3.902/include/verilated.cpp
g++  -I.  -MMD -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable     -ggdb -Wall -O3   -I/home/khiem/Desktop/Litex/litex/litex/build/sim/core   -c -o verilated_dpi.o /home/khiem/optimsoc/prebuilt/verilator-3.902/include/verilated_dpi.cpp
g++  -I.  -MMD -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable     -ggdb -Wall -O3   -I/home/khiem/Desktop/Litex/litex/litex/build/sim/core   -c -o verilated_vcd_c.o /home/khiem/optimsoc/prebuilt/verilator-3.902/include/verilated_vcd_c.cpp
/usr/bin/perl /home/khiem/optimsoc/prebuilt/verilator-3.902/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim.cpp Vsim_sim.cpp Vsim_VexRiscv.cpp Vsim_VexRiscv__1.cpp Vsim_VexRiscv__2.cpp Vsim__Slow.cpp Vsim_sim__Slow.cpp Vsim_VexRiscv__Slow.cpp Vsim_VexRiscv__1__Slow.cpp > Vsim__ALLcls.cpp
/usr/bin/perl /home/khiem/optimsoc/prebuilt/verilator-3.902/bin/verilator_includer -DVL_INCLUDE_OPT=include Vsim__Dpi.cpp Vsim__Trace.cpp Vsim__Syms.cpp Vsim__Trace__Slow.cpp Vsim__Trace__Slow__1.cpp > Vsim__ALLsup.cpp
g++  -I.  -MMD -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable     -ggdb -Wall -O3   -I/home/khiem/Desktop/Litex/litex/litex/build/sim/core   -c -o Vsim__ALLsup.o Vsim__ALLsup.cpp
g++  -I.  -MMD -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include -I/home/khiem/optimsoc/prebuilt/verilator-3.902/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -Wno-char-subscripts -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable     -ggdb -Wall -O3   -I/home/khiem/Desktop/Litex/litex/litex/build/sim/core   -c -o Vsim__ALLcls.o Vsim__ALLcls.cpp
/home/khiem/Desktop/Litex/litex/litex/build/sim/core/veril.cpp: In function ‘void litex_sim_init_tracer(void*, long int, long int)’:
/home/khiem/Desktop/Litex/litex/litex/build/sim/core/veril.cpp:52:8: error: ‘class VerilatedVcdC’ has no member named ‘set_time_unit’
   52 |   tfp->set_time_unit("1ps");
      |        ^~~~~~~~~~~~~
/home/khiem/Desktop/Litex/litex/litex/build/sim/core/veril.cpp:53:8: error: ‘class VerilatedVcdC’ has no member named ‘set_time_resolution’
   53 |   tfp->set_time_resolution("1ps");
      |        ^~~~~~~~~~~~~~~~~~~
make[1]: *** [Vsim.mk:74: veril.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: Leaving directory '/home/khiem/Desktop/Litex/build/sim/gateware/obj_dir'
make: *** [/home/khiem/Desktop/Litex/litex/litex/build/sim/core/Makefile:45: sim] Error 2
make: Leaving directory '/home/khiem/Desktop/Litex/build/sim/gateware'

I run litex_sim and got that error
How to fix it?
Thank!!

commented

Hi @KiemKhiem,

do you still have the issue? Is there something specific with the machine or verilator version? (try to use the latest verilator version if possible).