Physical constraint problem on tang_primer_20k
mmx-114514 opened this issue · comments
When I try to enable both hdmi and etnerbone on tang_primer_20k, the generated .cst physical constraint file has inconsistent voltages in the same bank: Bank 0 vccio(3.3) is locked by other constraint or embedded port, conflicting BANK_VCCIO set by 'hdmi_clk_p_obuf' : IO_TYPE = LVCMOS18 in the same bank. port, conflicting BANK_VCCIO set by 'hdmi_clk_p_obuf' : IO_TYPE = LVCMOS18 in the same bank How to solve this? Thank you for your help.
Yes... all the hdmi pins in the dock are pulled up using an external resistor:
Drop the IOStandard("LVCMOS18") on these pins:
Subsignal("hdp", Pins("CARD1:154"), IOStandard("LVCMOS18")),
Subsignal("cec", Pins("CARD1:152"), IOStandard("LVCMOS18")),
Subsignal("sda", Pins("CARD1:95"), IOStandard("LVCMOS18")),
Subsignal("scl", Pins("CARD1:97"), IOStandard("LVCMOS18")),
Hi @mmx-114514,
Can you share your build command to reproduce the issue? Thanks.
I Drop the IOStandard("LVCMOS18") on these pins.
Subsignal("hdp", Pins("CARD1:154"), #IOStandard("LVCMOS18")),
Subsignal("cec", Pins("CARD1:152"), #IOStandard("LVCMOS18")),
Subsignal("sda", Pins("CARD1:95"), #IOStandard("LVCMOS18")),
Subsignal("scl", Pins("CARD1:97"), #IOStandard("LVCMOS18")),