Wishbone L2 cache specs

[Nicolas Gaudin]

Hi,

What are the specifications of the Wishbone L2 cache ?

I would like to know the type of cache (direct-mapped or set associative).
If set associative, is it possible to change the number of ways and the replacement policy ?

Thanks

[josuah]

Only a clue rather than a full answer, but you might to want where, and in which configuration the wishbone.Cache() class is used:

https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone.py#L542

[Nicolas Gaudin]

Thanks for the clue, I'd had a look at this class.
From there, we can determine very little about the cache configuration (it's a write-back, and I assume it's a direct cache).

I am wondering how to modify the cache in order to implement my own L2 cache (generated automatically by the class or not) but with a different configuration.

[josuah]

As you can see below, which interconnect is picked is typically imported from the SoC's core itself (or rather its migen wrapper):

https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py#L21

So I suppose that you could

• either fork litex and import the changes from upstream as they come,
• either declare your own core and own interconnect/wishbone.py, then tune the wishbone.py

Maybe there are other hooks or locations to try to integrate the changes, but the LiteX newbie I am do not know about them.