ahegazy / HDL

This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..

hdl vhdl verilog systemverilog digitaldesign

Hardware description languages [HDL]

This repository contains scripts that I create through my digital design course.

Languages

Verilog
VHDL
SystemVerilog

Contents

ALU Arithmetic and logic unit that can perform addition, substation, bitwise operations like AND ,OR ,Shift Left, Shift Right, Rotate Left and Rotate Right.
SequenceDetector Detects a sequence of “110100” without any overlapping using FSM algorithm.
Queue Manager Monitors the client queue in front of the tellers.
UART Universal asynchronous receiver-transmitter.

Contribution ..

You can send a pull request for any edits or open an issue

About

This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..

hdl vhdl verilog systemverilog digitaldesign

Languages

Language:Verilog 100.0%