zynq vivado xilinx fpga cpp arm vhdl utt soc hardware-acceleration system-on-chip image-processing arm64 performance-evaluation plc programmable-logic-devices zc702

Zynq-TX-UTT

TX project about hardware acceleration performance of a Xilinx Zynq-7000 SoC ZC702 using image processing functions

In this report and associated Vivado source code, we try to evaluate the hardware acceleration performance of the Xilinx Zynq-7000 SoC ZC702 using image processing functions in C++, synthesised into HDL block IP with Vivado HLS and implemented on an ARM+FPGA interconnected architecture.

Authors

Pierre Avital - Initial work - p-avital
Julien Grave - Initial work - JulienGrv

See also the list of contributors who participated in this project.

License

This project is licensed under the GNU General Public License v3.0 - see the LICENSE.md file for details.

Acknowledgments

About

Hardware acceleration: performance evaluation of the Xilinx Zynq-7000 SoC ZC702

zynq vivado xilinx fpga cpp arm vhdl utt soc hardware-acceleration system-on-chip image-processing arm64 performance-evaluation plc programmable-logic-devices zc702

GNU General Public License v3.0

Languages

Language:VHDL 32.7%Language:C++ 27.2%Language:LLVM 24.4%Language:HTML 8.4%Language:C 3.0%Language:Coq 1.3%Language:Verilog 1.1%Language:V 0.8%Language:Ada 0.6%Language:Tcl 0.3%Language:Makefile 0.1%Language:Stata 0.0%Language:Scala 0.0%Language:Shell 0.0%Language:Assembly 0.0%Language:JavaScript 0.0%Language:SystemVerilog 0.0%Language:Forth 0.0%Language:CartoCSS 0.0%Language:TeX 0.0%Language:Batchfile 0.0%Language:Pascal 0.0%Language:1C Enterprise 0.0%Language:Ruby 0.0%