zewei

fpgadev

Development your FPGA accelerator on SmartNIC

a-week-in-wild-ai

360 view on ai/ml/dl applications

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Algorithmia

Algorithm and data-structure library for .NET 4.5.2+/Netstandard 2.0+. Algorithmia contains sophisticated algorithms and data-structures like graphs, priority queues, command, undo-redo and more.

anycore-riscv-src

The RTL source for AnyCore RISC-V

AWS-F1-Developer-Labs

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

basejump_stl_cornell

Our clone of https://github.com/bespoke-silicon-group/basejump_stl

beaglev

Computer-Science-Textbooks

Collect some CS textbooks for learning.

Cores-SweRV-EH1

SweRV EH1 core

Cores-SweRV-EH2

E203plus

upgrade to e203 (a risc-v core)

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

INC-ondemand

The Case For In-Network Computing On-Demand, EuroSys 2019

Main

Main page

openc910

OpenXuantie - OpenC910 Core

p4-guide

Guide to p4lang repositories and some other public info about P4

parallella-riscv

RISC-V port to Parallella Board

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

prog_dataplane_reading_list

The Programmable Data Plane: Reading List

pspin

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

PYNQ-Classification

Python on Zynq FPGA for Convolutional Neural Networks

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

scapytain

Scapytain is a web application that enables you to store, organise and run test campaigns on top of Scapy.

VG_RTL

All RTL codes of VG project

VG_Specification

All specifications of VG project

vivado-build-system

Vivado build system

vortex

zdma

Data transport between PL and PS on Xilinx ZYNQ -- MSc Thesis at TUC